Staff ASIC Design Verification Engineer

ASIC Design Verification Engineer Staff (L6 equivalent), scope across multiple teams 8-12 years

Other levels: ASIC Design Verification Engineer Senior ASIC Design Verification Engineer Principal ASIC Design Verification Engineer Lead ASIC Design Verification Engineer Junior ASIC Design Verification Engineer

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The job description

Tech stack. SystemVerilog/UVM at scale, subsystem verification, formal apps (Jasper/VC Formal), emulation workflows, regression infrastructure, coverage analytics

About the role

You will operate across multiple design teams at a fabless semiconductor company, taking on the verification problems that no single block owner can solve alone: subsystem integration, cross-clock-domain behavior, and the gnarliest debug in the program. You will be the engineer other engineers call when regressions stall and tapeout risk is unclear. Your charter is breadth: raising verification quality and consistency everywhere you touch, and leaving stronger engineers behind you.

What you will achieve

Close subsystem-level verification for interfaces spanning three or more blocks, delivering integration test plans with measurable coverage of cross-block scenarios and signoff criteria the program trusts.
Drive the program's hardest debug efforts to RTL root cause, resolving the top escape-risk bugs that block milestone signoff and documenting the patterns so teams avoid repeats.
Deliver coverage and regression analytics that give program leadership a trustworthy, quantified view of tapeout readiness each week, replacing gut feel with data.
Reduce verification redundancy by identifying shared verification IP and environment components across teams and driving their reuse, cutting duplicated effort measurably.
Raise the technical level of multiple teams by leading deep-dive debug reviews and coaching senior engineers on advanced techniques (formal, emulation, coverage-driven closure).

What you will bring

Must-haves

8 to 12 years of ASIC verification experience with ownership spanning multiple blocks or full subsystems through tapeout.
Mastery of UVM/SystemVerilog with a portfolio of complex testbenches (multi-clock, multi-power-domain, or high-throughput datapath designs).
Proven ability to debug system-level failures across RTL, testbench, and firmware boundaries without losing the thread.
Hands-on experience with formal verification and emulation as complements to simulation-based verification, knowing when each pays off.
Strong grasp of microarchitecture: you read specs and RTL with a designer's eye and spot verification gaps before they become escapes.
Influence without authority: a record of aligning multiple teams on shared verification practices and schedules.
Clear technical writing and review skills: your plans, signoff documents, and debug reports set the standard others follow.

Nice-to-haves

Experience with post-silicon debug collaboration, connecting lab failures back to verification gaps.
Knowledge of performance verification or power-aware verification techniques.
Familiarity with continuous integration practices adapted to hardware regression flows.
Exposure to technical program leadership or cross-functional risk reviews.