Senior ASIC Design Verification Engineer

ASIC Design Verification Engineer Senior (L5 equivalent) 5-8 years

Other levels: ASIC Design Verification Engineer Principal ASIC Design Verification Engineer Staff ASIC Design Verification Engineer Lead ASIC Design Verification Engineer Junior ASIC Design Verification Engineer

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NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. SystemVerilog, UVM, verification planning, Synopsys VCS, Cadence Xcelium, Jasper formal, CDC/RDC analysis, Perl/Python automation

About the role

You will own design verification for a full block or cluster at a fabless chip company where tapeout dates are immovable and silicon quality is the brand. You will set the verification strategy for your area, architect testbenches that scale across design spins, and act as the technical conscience of the RTL team: finding the bugs that matter early and driving them to RTL closure. Your influence extends beyond your own code to the engineers you mentor and the signoff standards you enforce at every review.

What you will achieve

Architect reusable UVM environments that survive multiple design spins, holding regression bring-up under two weeks per major RTL drop and eliminating rework between spins.
Deliver tapeout-ready blocks with zero known functional escapes, measured by a documented signoff checklist you define, maintain, and defend at milestone reviews.
Drive code and functional coverage to 100 percent and 95 percent respectively across your scope, with every waiver reviewed, justified in writing, and approved by design leadership.
Cut escape-prone corner cases by integrating formal property checks on critical control paths, catching at least one deep bug per program before silicon that simulation was unlikely to reach.
Reduce cross-team debug churn by publishing clear verification plans, bug triage SLAs, and design-for-verification guidelines that your designers actually follow, and by holding the line on them.

What you will bring

Must-haves

5 to 8 years of ASIC design verification experience with at least two full tapeouts in a UVM/SystemVerilog flow, including ownership through signoff.
Proven ownership of block or cluster verification strategy: plans, schedules, coverage closure, and the final signoff recommendation.
Deep expertise in constrained-random verification, functional coverage modeling, and SVA assertion development for complex control and datapath logic.
Working experience with formal verification tools on control logic and with CDC/RDC analysis integrated into the verification loop.
Demonstrated ability to debug the hardest failures (data corruption, protocol deadlocks, reset sequencing) down to RTL root cause without hand-holding.
History of mentoring junior engineers and raising the bar on testbench quality through rigorous code reviews.
Sound schedule judgment: you scope verification effort realistically, flag risk early with data, and replan credibly when RTL slips.

Nice-to-haves

Experience with low-power verification (UPF) or mixed-language (VHDL) designs.
Familiarity with emulation platforms for accelerating long software-driven scenarios.
Contributions to methodology improvements adopted beyond your own team.
Exposure to post-silicon debug that sharpened your pre-silicon test planning.