ASIC Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

Other levels: Senior ASIC Design Verification Engineer Principal ASIC Design Verification Engineer Staff ASIC Design Verification Engineer Lead ASIC Design Verification Engineer Junior ASIC Design Verification Engineer

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Qualcomm

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Synopsys

Cadence

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The job description

Tech stack. SystemVerilog, UVM, Synopsys VCS, Siemens Questa, Cadence Xcelium, SVA assertions, coverage-driven verification, Python scripting

About the role

You will join the design verification team at a fabless semiconductor company taping out high-performance ASICs on aggressive schedules. You will sit shoulder to shoulder with RTL designers, not across an org chart, co-owning verification from the first microarchitecture review through tapeout signoff. Your job is to close the loop: every bug you find becomes an RTL fix that you validate before it can reach silicon, and your coverage numbers are the evidence the program trusts at every milestone.

What you will achieve

Deliver block-level SystemVerilog/UVM testbenches that reach 100 percent functional coverage on your assigned blocks within the project milestone schedule, with coverage models reviewed and approved by the block designers.
Drive regression suites to 98 percent or better pass rates ahead of each tapeout checkpoint, triaging new failures to RTL bugs versus testbench issues within 48 hours while keeping a clean, prioritized bug backlog.
Ship SVA assertion plans co-authored with designers that catch protocol violations at their source, keeping post-synthesis bug escapes at zero on your blocks across the full program.
Cut debug turnaround time by building self-checking scoreboards and reference models that pinpoint failing transactions in minutes rather than days, and by documenting debug playbooks your teammates reuse.
Reduce verification risk by feeding design-for-verification feedback (controllability, observability, clocking and reset hooks) into RTL reviews before code freeze, preventing the untestable corners that cause late escapes.

What you will bring

Must-haves

2 to 5 years of digital design verification experience on ASIC or FPGA programs using SystemVerilog and UVM, with at least one project carried through a major milestone.
Hands-on ownership of block-level testbench development: drivers, monitors, sequencers, scoreboards, and coverage collection built from scratch or substantially extended.
Strong command of SVA and constrained-random stimulus, with a track record of bug finds that changed RTL rather than just testbench tweaks.
Experience running and debugging regressions on at least one commercial simulator (VCS, Questa, Xcelium) through to closure, including failure triage and waiver justification.
Working knowledge of digital design fundamentals: synchronous logic, clock-domain crossing, FIFO and handshake protocols, and reset strategies.
Comfort reading RTL and debug waveforms to isolate root cause jointly with designers, communicating findings clearly in bug reports and reviews.
Disciplined verification habits: version control, reproducible regressions, and documentation that lets another engineer pick up your work without friction.

Nice-to-haves

Exposure to formal property checking or gate-level simulation as a complement to block-level UVM work.
Python or Perl scripting for regression automation, coverage analysis, and results dashboards.
Experience with CDC or lint tooling as part of a signoff flow.
Familiarity with low-power design concepts (clock gating, power domains) from a verification perspective.