Lead ASIC Design Verification Engineer

ASIC Design Verification Engineer Lead, technical leadership of a small team 7-10+ years

Other levels: ASIC Design Verification Engineer Senior ASIC Design Verification Engineer Principal ASIC Design Verification Engineer Staff ASIC Design Verification Engineer Junior ASIC Design Verification Engineer

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NVIDIA

Qualcomm

AMD

Broadcom

Synopsys

Cadence

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The job description

Tech stack. SystemVerilog/UVM, verification project planning, regression triage leadership, Synopsys VCS, coverage management, Jira or equivalent tracking

About the role

You will lead a small design verification team at a semiconductor company where you remain hands-on with the hardest technical work while owning your team's execution. You will turn program milestones into verification plans, assign and unblock work, and carry the team's signoff commitment to tapeout. You are the bridge between engineering leadership's schedule and your team's day-to-day reality, accountable for both the technical quality and the human growth of your engineers.

What you will achieve

Ship your team's blocks to tapeout on schedule with zero functional escapes, owning the signoff decision and its evidence for every block in your scope.
Build a verification plan for each program phase that maps coverage targets, regression milestones, and staffing to the RTL delivery schedule, updated as reality changes.
Drive your team's regression health to sustained 98 percent-plus pass rates, with triage rotations that resolve new failures within one business day.
Grow your engineers: run structured code reviews, pair on hard debug, and develop at least two team members toward independent block ownership each year.
Cut verification cycle time by standardizing your team's testbench patterns, coverage models, and debug playbooks across blocks, so knowledge compounds instead of evaporating.

What you will bring

Must-haves

7 to 10+ years of ASIC design verification experience, including at least two tapeouts with block or cluster ownership through signoff.
Prior technical leadership: mentoring, work assignment, or informal team lead experience with demonstrated results in execution and growth.
Expert-level SystemVerilog/UVM skills and a strong record of coverage closure under real schedule pressure.
Excellent debug skills across RTL, testbench, and protocol levels, with the ability to coach others through the same process rather than just fixing it yourself.
Clear, honest communication: you surface schedule risk early with data and options, never surprises at the milestone review.
Fluency in verification planning: effort estimation, milestone tracking, and risk-based prioritization across competing demands.
People judgment: you give direct feedback, run effective reviews, and build a team culture where quality and candor reinforce each other.

Nice-to-haves

Experience hiring and onboarding verification engineers.
Exposure to formal or emulation-based verification to guide tool adoption on your team.
Background in a second verification domain (low-power, mixed-signal, or post-silicon) that broadens your team's coverage.
Familiarity with agile or structured planning methods adapted to hardware schedules.