Staff Mixed Signal Design Engineer

About the role

You will be the mixed-signal technical lead spanning multiple design teams at a fabless semiconductor company shipping complex SoCs. Staff engineers here own the hard cross-team problems: the ADC whose reference couples into the PLL, the power domain sequencing that nobody fully specified, the top-level floorplan choice that makes or breaks analog isolation. This role matters because your reach across teams turns a collection of good blocks into one working chip. Your decisions will be documented as architecture records the whole organization can trace, and you will report to the analog director while working shoulder to shoulder with digital, packaging, and product engineering.

What you will achieve

• Lead mixed-signal integration across two or more teams: define top-level analog architecture, power domain plans, and signal-integrity budgets that every block team designs against.
• Deliver complex blocks (high-resolution ADC, wideband PLL, or high-speed interface) with first-silicon success, hitting datasheet specs with margin verified across corners and Monte Carlo.
• Reduce cross-team analog issues by owning the top-level AMS verification plan: real-number models for every analog block, interface assertion checks, and power-sequence verification before tapeout.
• Drive measurable power and noise improvements at the chip level, for example 3-6 dB better ADC SNR through substrate isolation and reference routing discipline you specify and enforce.
• Mentor senior and junior designers across teams, running cross-functional design reviews that catch integration problems while they are still cheap to fix.

What you will bring

Must-haves

• 8-12 years of analog/mixed-signal design with multiple tapeouts and a record of first-silicon success on complex blocks.
• Demonstrated cross-team scope: owning integration, interfaces, or top-level architecture across more than one design team.
• Deep expertise in at least one analog domain plus working fluency in adjacent ones (converters, clocking, power, I/O) so you can review blocks outside your specialty.
• Mastery of the full sign-off flow: extracted corners, statistical analysis, EM/IR, ESD/latch-up, reliability, and mixed-signal top-level checks.
• Strong lab bring-up and debug skills at the system level, tracing chip-level failures to block-level or integration root causes.
• Clear technical communication: writing specs, interface documents, and review notes that multiple teams can build from.

Nice-to-haves

• Advanced-node (7nm and below) tapeout experience with finFET-specific analog effects.
• Experience with substrate noise modeling and isolation strategy at the top level.
• Familiarity with chiplets, UCIe, or die-to-die analog interfaces.