Mixed Signal Design Engineer

About the role

You will join a fabless semiconductor company whose analog and digital teams share one tapeout deadline, and you will be the engineer who makes the two sides actually work together. The team designs mixed-signal subsystems (data converters, voltage references, clocking, and I/O) that land on every product the company ships. This role matters because one well-executed ADC, LDO, or PLL block can unlock the performance headroom an entire SoC roadmap depends on.

What you will achieve

• Ship two to three tapeout-ready analog/mixed-signal blocks per year (ADC, DAC, bandgap, LDO, or comparator), delivering schematic, layout review, parasitic-extracted sign-off, and test plans on schedule.
• Drive block-level power and area to at or under the allocated budget, with silicon-measured figure of merit landing within 15% of pre-silicon simulation on first silicon.
• Reduce mixed-signal integration risk by writing Verilog-AMS behavioral models of your blocks that the digital team can simulate at the top level at least six weeks before tapeout.
• Own your blocks from specification through silicon bring-up: define the spec with the system architect, close corner and Monte Carlo sign-off, and debug first silicon in the lab with your own bench measurements.
• Cut top-level AMS co-simulation failures by delivering real-number models that catch digital/analog interface mismatches (clocking, resets, power sequencing) before tapeout rather than in the lab.

What you will bring

Must-haves

• 2-5 years designing analog/mixed-signal circuits in CMOS, including at least one of ADCs, DACs, amplifiers, references, comparators, or PLLs.
• Fluency in Cadence Virtuoso schematic and simulation flows, including corner analysis, Monte Carlo, and mismatch analysis in Spectre.
• Hands-on lab experience bringing up your own silicon: oscilloscopes, spectrum analyzers, and logic analyzers used to close the loop between simulation and measurement.
• Understanding of analog layout parasitics and the ability to review layouts with Calibre DRC/LVS/PEX and give layout engineers actionable, specific feedback.
• Working knowledge of Verilog-AMS or SystemVerilog real-number modeling so your blocks can participate in top-level mixed-signal simulation.
• At least one completed tapeout as a block owner, so you know what sign-off rigor actually costs in schedule and effort.

Nice-to-haves

• Familiarity with finFET PDKs or advanced-node analog layout and matching practices.
• Experience with on-chip calibration, trimming, or self-test techniques.
• Scripting in Python or SKILL to automate simulation sweeps, regression runs, and results parsing.