Staff CPU Design Engineer

About the role

You will operate as a staff design engineer with influence spanning multiple CPU design teams at a semiconductor company. Staff designers work on the problems that cross team boundaries: the interfaces between blocks that nobody owns cleanly, the timing paths that span hierarchies, the methodology gaps that slow everyone down, and the junior teams that need experienced guidance. Your technical credibility lets you align teams, unblock programs, and raise quality everywhere you engage.

What you will achieve

• Drive design alignment across multiple CPU block teams, ensuring consistent coding standards, interface disciplines, and quality bars so independently designed blocks integrate cleanly.
• Resolve cross-team design issues such as interface protocol mismatches, multi-block timing paths, and clocking or reset architecture questions with technically sound, fairly reached decisions.
• Build reusable design infrastructure including verification IP, check flows, timing utilities, or automation that measurably improves productivity across teams.
• Lead timing closure for critical multi-block paths and top-level integration, coordinating designers and physical design engineers toward predictable results.
• Mentor designers across teams through reviews and direct guidance, spreading best practices and developing talent beyond your own organization.
• Champion methodology improvements such as advanced lint flows, formal verification adoption, or ML-assisted design techniques, measuring their impact on quality and schedule.

What you will bring

Must-haves

• 8 to 12 years of experience in CPU or complex ASIC design with multiple tapeouts across different blocks or programs.
• Proven ability to influence and align multiple teams through technical credibility rather than formal authority.
• Deep expertise in RTL design, timing closure, and the physical design interaction, with the ability to debug the hardest cross-boundary problems.
• Experience building design infrastructure, flows, or methodology adopted beyond a single team.
• Strong understanding of the full implementation cycle from microarchitecture through synthesis, place and route, and silicon validation.
• Excellent communication skills for cross-functional technical leadership and honest status reporting.
• Sound judgment about where to invest effort for maximum program impact.

Nice-to-haves

• Experience with chiplet-based designs or multi-die integration challenges.
• Familiarity with advanced verification methodologies and their integration with design flows.
• Prior technical leadership spanning multiple design teams.