Senior CPU Design Engineer

About the role

You will serve as a senior CPU design engineer at a semiconductor company, owning the most challenging logic blocks in the processor and setting the technical standard for the design team. Senior designers take on the blocks where others struggle: deep pipelines with aggressive timing, complex control with subtle corner cases, and power-critical units where every microwatt matters. You will design, verify, and close timing on these blocks while mentoring junior engineers and improving the team's methodology.

What you will achieve

• Own the design of complex CPU blocks such as out-of-order schedulers, load-store units, or branch predictors from microarchitecture specification through RTL, verification, timing closure, and silicon validation.
• Achieve first-pass timing closure on aggressive frequency targets through skilled microarchitecture-aware RTL design, pipeline balancing, and proactive critical path management.
• Drive block-level and cluster-level verification to coverage and quality targets, designing testbenches and verification strategies that find deep corner-case bugs before integration.
• Mentor junior design engineers through code reviews, design guidance, and debugging help, raising the quality bar for the entire team's output.
• Lead the resolution of the hardest bugs found in verification, emulation, or silicon, applying systematic root-cause analysis and implementing robust fixes.
• Improve design methodology by introducing better coding practices, check flows, or automation that measurably reduces bugs or schedule risk across the team.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU or complex ASIC logic design with multiple tapeouts.
• Expert-level SystemVerilog design skills with a track record on timing-critical, complex control logic.
• Deep microarchitecture knowledge spanning pipelines, out-of-order execution, memory subsystems, and their implementation tradeoffs.
• Strong verification skills including testbench architecture, coverage-driven methods, and debugging of the hardest failures.
• Proven timing closure experience on high-frequency designs with understanding of physical design interaction.
• Fluency in at least one major ISA and its implications for logic design.
• Technical leadership ability: you raise the team's standards through reviews, mentoring, and example.

Nice-to-haves

• Experience with emulation platforms for pre-silicon validation.
• Knowledge of advanced low-power techniques including adaptive voltage scaling and fine-grained power gating.
• Familiarity with formal verification and its application to complex control logic.