CPU Design Engineer

CPU Design Engineer Mid-level (L4 equivalent) 2-5 years

Other levels: Senior CPU Design Engineer Principal CPU Design Engineer Staff CPU Design Engineer Lead CPU Design Engineer Junior CPU Design Engineer

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The job description

Tech stack. SystemVerilog, CPU microarchitecture, RTL design, simulation and debug, synthesis, lint and CDC checks, Arm and RISC-V ISAs, Python and TCL scripting, timing analysis basics

About the role

You will design digital logic for CPUs at a semiconductor company, turning architecture specifications into working RTL that becomes silicon. CPU design engineers own blocks of the processor from specification through implementation: they write SystemVerilog, verify their logic functionally, close timing with physical design, and support silicon bring-up. Your RTL will execute billions of instructions per second in products used around the world, and the quality of your design work shows up directly in the product's performance, power, area, and schedule.

What you will achieve

Design and implement CPU functional blocks such as pipeline stages, execution units, or control logic in SystemVerilog, meeting the architecture specification's functional, timing, power, and area requirements.
Deliver block-level verification including testbench development, directed and constrained-random testing, and coverage closure, reaching the coverage and bug-rate targets required for integration.
Close timing on your blocks in partnership with physical design, understanding critical paths deeply and restructuring logic proactively rather than relying on synthesis alone to fix problems.
Run and resolve lint, CDC, RDC, and low-power checks cleanly, treating design quality checks as part of design rather than a hurdle before tapeout.
Support full-chip integration, system-level verification, and post-silicon debug, diagnosing issues in your blocks quickly and implementing fixes or workarounds under pressure.
Document your designs thoroughly with block specifications, interface definitions, and design notes that make your work maintainable by the broader team.

What you will bring

Must-haves

2 to 5 years of experience in digital logic design with CPU, SoC, or complex ASIC exposure.
Strong SystemVerilog skills for both design and testbench development, with clean, synthesizable coding style.
Solid understanding of CPU microarchitecture fundamentals: pipelining, hazards, arbitration, FIFOs, and state machine design.
Experience with simulation-based verification including debug of complex failures using waveforms and systematic reasoning.
Familiarity with synthesis, static timing analysis concepts, and the physical realities that constrain logic design.
Scripting ability in Python, TCL, or similar for automating design and verification workflows.
Ownership mentality: you treat your blocks as your product and drive them to completion without being chased.

Nice-to-haves

Experience with low-power design techniques such as clock gating, power gating, and multi-voltage domains.
Knowledge of Arm or RISC-V ISAs and their hardware implications.
Exposure to formal verification methods for control logic.