Staff Analog IC Design Engineer

About the role

You will join a fabless semiconductor company as a staff analog IC design engineer with scope across multiple product teams. Your work sits at the boundaries where analog blocks meet digital logic, package, and board: the interfaces where the most painful chip-level failures originate. This role matters because individual teams can each tape out clean blocks and still fail at integration; you are the engineer who makes the whole chip work together. Your influence multiplies because every product team ships through your integration signoff, making you the connective tissue of the silicon organization.

What you will achieve

• Own chip-level analog integration for flagship SoCs, driving power, substrate, and package co-design decisions that protect analog performance at scale
• Define and enforce analog-digital interface contracts (timing, noise budgets, supply domains) that eliminate integration re-spins across teams
• Lead cross-team design reviews for high-risk blocks, catching coupling, sequencing, and verification gaps before layout starts
• Deliver reusable analog IP with documentation and verification collateral strong enough for drop-in reuse by teams you never meet
• Cut tapeout risk by building chip-level AMS verification plans that prove out startup, mode transitions, and fault behavior before silicon
• Mentor senior and mid-level designers across teams, spreading best practices in noise isolation, floorplanning, and review discipline
• Establish analog IP reuse metrics and quality gates that the company uses to measure and improve cross-team IP adoption year over year

What you will bring

Must-haves

• 8-12 years of analog IC design with several shipped SoCs where you owned significant analog content or integration
• System-level thinking: you reason about supplies, clocks, substrate, and package as one coupled problem, not separate domains
• Mastery of Cadence Virtuoso and Spectre plus AMS/analog-digital co-simulation at the top level
• A history of finding and fixing chip-level issues: coupling, IR drop, sequencing, or test escapes that others could not root-cause
• Strong written and verbal communication: your review feedback and interface specs are models other teams copy
• Demonstrated mentorship of engineers across team boundaries, with mentees who grew into independent designers
• B.S. or M.S. in Electrical Engineering with depth in both analog circuits and mixed-signal systems

Nice-to-haves

• Experience with advanced packaging effects: chiplets, 2.5D interposers, or flip-chip supply networks
• Familiarity with DFT and analog test strategy for high-volume production
• Prior work on power management or clocking architectures at the SoC level