Senior ASIC Verification Engineer

About the role

You will join a fabless semiconductor company building next-generation compute silicon, where senior verification engineers own the verification plans that decide tapeout readiness. This role goes beyond writing testbenches: you set verification strategy for complex blocks or subsystems, mentor less experienced engineers, and drive the cross-functional closure process with design, architecture, and physical design teams. You will be the engineer others bring their hardest debug problems to, the reviewer whose feedback raises testbench quality across the team, and the voice in signoff meetings that says whether the design is truly ready. When a tapeout date is at risk, your judgment on what is verified enough is what the team trusts, and your track record of clean silicon is what earns that trust.

What you will achieve

• Own verification plans for complex blocks or subsystems and drive them to full signoff, closing functional and code coverage to agreed targets two weeks before RTL freeze.
• Lead debug on the hardest failures in the project, root-causing issues that span testbench, RTL, and architecture within days rather than weeks.
• Mentor two to three verification engineers, reviewing their testbench code and verification plans to raise the bar across the team.
• Reduce regression turnaround time by 40 percent by restructuring suites, parallelizing runs, and eliminating redundant or low-value tests.
• Drive zero critical bug escapes on the blocks you own across at least one full tapeout cycle, measured by post-silicon issue reports.

What you will bring

Must-haves

• 5 to 8 years of ASIC verification experience, including at least two full tapeouts with block or subsystem ownership.
• Expert-level UVM skills: architecting reusable testbench environments, layered sequences, and reference-model-based scoreboards.
• Deep SVA expertise for both simulation checkers and formal property specifications.
• Track record of writing verification plans that map features to coverage and hold up under signoff review.
• Strong debug skills across waveforms, transaction logs, and gate-level simulations.
• Experience coordinating verification closure with design, DFT, and physical design teams under tapeout pressure.
• Clear technical writing for bug reports, verification plans, and signoff documentation.

Nice-to-haves

• Experience with low-power verification including UPF-driven simulation and power-aware checks.
• Familiarity with emulation platforms for pre-silicon software validation.
• Prior work on high-speed interface protocols such as PCIe, DDR, or Ethernet.
• Experience with safety-critical verification flows such as ISO 26262.