Junior ASIC Verification Engineer

About the role

You will join the verification team of a fabless semiconductor company as an entry-level engineer, learning the craft of pre-silicon verification alongside experienced mentors. The team verifies complex ASIC blocks headed for datacenter and networking products, and you will start by writing directed tests, running regressions, and debugging failures with guidance from senior engineers. Every task is a lesson: each regression you triage teaches you to read waveforms, each bug you file teaches you what designers need, and each UVM component you build adds to a skill set that compounds quickly. This role is built for growth, with structured mentorship, code reviews on everything you write, and a clear path from running other people's tests to owning pieces of a UVM testbench yourself within your first year.

What you will achieve

• Write and debug directed SystemVerilog tests that exercise new RTL features, contributing passing tests to the regression suite within your first three months.
• Run nightly regressions and triage failures, correctly distinguishing testbench issues from genuine RTL bugs in at least 90 percent of cases by month six.
• Build your first UVM components (a simple driver, monitor, or sequence) under mentorship and integrate them into a production testbench.
• Add functional coverage points for assigned features and help drive them toward closure during the coverage push before RTL freeze.
• File clear, reproducible bug reports with waveforms and log evidence that designers can act on without follow-up questions.

What you will bring

Must-haves

• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field with coursework in digital design and verification.
• Foundational knowledge of SystemVerilog, including classes, randomization, and interfaces, from coursework or internships.
• Basic understanding of the UVM methodology: agents, drivers, monitors, and sequences at a conceptual level.
• Familiarity with digital logic design, finite state machines, and synchronous design principles.
• Comfort working in a Linux environment with the command line, Makefiles, and version control.
• Strong debugging temperament: patience with waveforms, curiosity about root causes, and persistence through long failure logs.
• Clear written communication for bug reports and status updates.

Nice-to-haves

• Internship or project experience with RTL simulation in VCS, Xcelium, or Questa.
• Exposure to scripting in Python or Tcl for simple automation tasks.
• Coursework or projects involving assertion-based verification or formal methods.
• Personal projects demonstrating SystemVerilog or digital design skills.