Lead ASIC Verification Engineer

ASIC Verification Engineer Lead, technical leadership of a small team 7-10+ years

Other levels: ASIC Verification Engineer Senior ASIC Verification Engineer Principal ASIC Verification Engineer Staff ASIC Verification Engineer Junior ASIC Verification Engineer

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The job description

Tech stack. SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, SVA, Python, project planning, code review leadership, regression management

About the role

You will technically lead a small verification team at a fabless semiconductor company taping out aggressive, schedule-driven silicon. As lead, you own the verification plan and schedule for your area: you break the work into tasks, assign them across the team, run reviews, and stay hands-on with the hardest blocks yourself. This is a player-coach role. You write testbench code and debug the toughest failures while making sure the engineers around you are productive, unblocked, and growing. You will run the daily triage that keeps regressions green, the reviews that keep quality high, and the planning that keeps the schedule honest. Your team will hit its tapeout milestones because you balance technical depth with the organizational discipline that turns individual talent into reliable delivery.

What you will achieve

Deliver the verification plan and schedule for your block cluster, hitting every coverage and bug burn-down milestone on the tapeout calendar.
Keep a team of three to six verification engineers productive by clearing blockers daily and rebalancing work as RTL drops land.
Personally own the highest-risk blocks in your area, driving them to signoff-grade coverage without slipping the team schedule.
Raise team output quality by running rigorous testbench code reviews and verification plan reviews, cutting review-escaped defects by 40 percent.
Grow the engineers on your team through structured mentorship, with at least two team members measurably expanding their scope each year.

What you will bring

Must-haves

7 or more years of ASIC verification experience, including prior technical leadership or informal mentorship of other engineers.
Strong UVM and SystemVerilog skills with a record of shipping production testbenches on schedule.
Experience breaking verification work into plans, estimates, and task assignments across a small team.
Proven debug leadership: triaging team-wide regression failures and directing debug effort where it matters most.
Ability to run effective design reviews, code reviews, and signoff reviews with design counterparts.
Clear status communication to project management, including honest risk and schedule assessments.
Hands-on SVA and coverage-closure skills you can apply directly to the hardest blocks.

Nice-to-haves

Experience staffing or interviewing verification engineers.
Familiarity with Agile or sprint-based planning adapted to hardware schedules.
Exposure to formal verification for supplementing simulation coverage.
Prior experience coordinating with multi-site verification teams.