Junior CPU Design Engineer

About the role

You will join a CPU design team at a semiconductor company as a junior designer, learning professional RTL design while contributing to real blocks from your first months. Junior designers implement well-defined logic under senior guidance, build testbenches, debug failures systematically, and absorb the discipline of quality-driven hardware design. This is a deliberate apprenticeship with real responsibility: you will receive close mentorship, regular feedback, and progressively harder assignments, and your growth into an independent designer who owns blocks end to end is an explicit goal of the role.

What you will achieve

• Implement assigned logic blocks or sub-blocks in SystemVerilog under senior guidance, meeting functional requirements with clean, synthesizable coding style that passes team reviews.
• Build and extend block-level testbenches, write directed tests targeting specified behaviors, and debug failures systematically using waveforms, assertions, and analytical reasoning.
• Run lint, CDC, and synthesis checks on your blocks and resolve violations thoroughly, learning to treat design quality as integral to design rather than an afterthought or a pre-tapeout hurdle.
• Contribute to coverage closure by writing tests that target uncovered scenarios, steadily improving the verification completeness of your blocks and learning what thorough verification looks like.
• Document your designs with block diagrams, interface descriptions, and design notes that meet the team's standards and genuinely help future maintainers understand your work.
• Grow rapidly through code reviews, mentorship, and post-mortems, progressing from implementing well-defined tasks to owning small blocks independently within the first year.

What you will bring

Must-haves

• 0 to 2 years of relevant experience, or a strong degree in electrical or computer engineering with substantial digital design coursework and hands-on projects.
• Solid digital design fundamentals: combinational and sequential logic, finite state machines, pipelining concepts, and timing basics.
• Basic SystemVerilog or Verilog skills with the ability to write synthesizable RTL and simple testbenches.
• Programming ability in Python or similar for scripting, automation, and data analysis.
• Genuine enthusiasm for processor design and the patience for meticulous, detail-oriented hardware work.
• Clear communication and the humility to ask questions early, accept critique gracefully, and learn from mistakes.
• Reliability and work ethic: you finish assignments, communicate status proactively, and seek help before small problems become big ones.

Nice-to-haves

• Coursework or projects in computer architecture covering pipelines, caches, or branch prediction.
• Familiarity with RISC-V and FPGA-based processor projects.
• Internship experience in digital design or verification.
• Exposure to version control workflows and collaborative hardware development.