UVM Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. UVM (advanced), SystemVerilog, UVM Register Layer (RAL), verification IP integration, TLM modeling, simulator performance tuning

About the role

You will be the methodology specialist on the design verification team of a semiconductor company, the engineer who makes UVM environments correct, reusable, and fast. While block owners focus on features, you focus on the machinery: testbench architecture, register models, reusable VIP, and simulation performance. Designers rely on your environments to validate every RTL change, so your code quality directly sets the pace of the program, and your standards shape how every team builds. Your libraries and standards quietly determine whether the program's verification scales or collapses under its own weight.

What you will achieve

Deliver a standardized UVM base-class library (agents, sequences, scoreboard frameworks) adopted across at least three block teams, cutting new testbench bring-up time in half.
Ship accurate UVM Register Layer models for every block in your scope, validated against RTL with front-door and back-door sequences at 100 percent register coverage.
Drive simulation throughput up by profiling and optimizing testbench bottlenecks, targeting 2x or better performance on the longest-running regressions.
Reduce environment bugs by enforcing coding standards and review checklists for UVM code, keeping environment-caused regression noise under 5 percent of total failures.
Build reusable verification IP for standard protocols (AXI, APB, UART, SPI) that new programs instantiate rather than rebuild, with documentation teams actually use.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with deep, hands-on UVM expertise well beyond basic agent development.
Mastery of the UVM Register Layer: modeling, prediction, coverage, and integration with block-level and SoC-level environments.
Strong SystemVerilog skills including TLM, phasing, factory overrides, and configuration mechanisms used correctly, not cargo-culted.
Experience integrating third-party verification IP and adapting it to project-specific protocols and corner cases.
Understanding of simulator performance: compile flows, optimization switches, and the testbench constructs that silently slow simulation.
Teaching ability: you can explain UVM concepts to block owners and raise the methodology level of the whole team.
Rigor about backward compatibility: your shared libraries never break existing users on upgrade.

Nice-to-haves

Familiarity with UVM-to-formal or UVM-to-emulation reuse strategies.
Scripting skills for environment generation or regression flow automation.
Experience with portable stimulus (PSS) or other next-generation methodology.
Knowledge of CI practices for continuously validating shared verification libraries.