Top-Level Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, top-level testbenches, pad/pin-level modeling, clock/reset verification, Synopsys VCS, gate-level simulation, Python

About the role

You will verify the chip at its boundary at a fabless semiconductor company, owning the top-level testbench that proves the assembled SoC works as a single device. Top-level verification sits above block and subsystem testing: pin-level connectivity, clock and reset trees, pad configurations, and the final full-chip regressions that gate tapeout. When the question is whether the chip as taped out will work in the package on the board, your testbench is the answer. You will coordinate the final verification campaign across every team in the project, catch the integration mistakes that only exist at full-chip scope, and carry the signoff responsibility for the device as a whole. Tapeout confidence starts at the top level, and you own it.

What you will achieve

Build and maintain the top-level testbench, verifying pin-level behavior, pad multiplexing, and external interface connectivity across the full chip.
Verify clock and reset architecture end to end: clock switching, reset sequencing, and domain crossings at the top level with zero signoff violations.
Drive the final tapeout regression campaign, coordinating full-chip runs across block, subsystem, and SoC teams to a clean signoff.
Catch top-level integration bugs (misconnected ports, wrong tie-offs, reset-domain errors) before tapeout, with zero such escapes to silicon.
Reduce full-chip simulation turnaround by 35 percent through hierarchical testbench techniques and selective re-verification after ECOs, while preserving the signoff confidence of a complete regression.

What you will bring

Must-haves

2 to 5 years of verification experience including full-chip or top-level testbench work.
Strong SystemVerilog and UVM skills applied at chip-level scope, including pin-level stimulus and checking.
Understanding of chip-level infrastructure: clock trees, reset networks, power domains, and pad rings.
Experience verifying connectivity and integration at the top level, including tie-off and strap-pin checking.
Familiarity with gate-level simulation at full-chip scope for final signoff confidence.
Ability to coordinate verification activities across multiple block and subsystem teams.
Scripting skills for managing large, multi-team regression campaigns.

Nice-to-haves

Experience with formal connectivity checking tools at the top level.
Knowledge of package and board-level considerations that affect top-level verification.
Exposure to post-silicon debug to understand which top-level bugs escape.
Familiarity with IR drop and power-integrity concerns at chip level.