SystemVerilog Verification Engineer

About the role

You will be the SystemVerilog craftsman on the verification team of a fabless semiconductor company, owning the quality of the testbench code itself. This role centers on language mastery: advanced randomization, interfaces and clocking blocks, DPI-C integration, and testbench architectures that are fast, maintainable, and correct. When simulation performance stalls or a testbench behaves nondeterministically, you are the engineer who reads the language reference, finds the semantic subtlety, and fixes it at the source. You will build the packages, utilities, and infrastructure that every testbench in the project depends on, and your code reviews will teach the team to write SystemVerilog that is both expressive and efficient. Great verification starts with great testbench code, and yours sets the standard.

What you will achieve

• Deliver high-performance SystemVerilog testbench infrastructure with simulation throughput improved by 30 percent through efficient coding practices and process management.
• Eliminate nondeterministic testbench behavior (race conditions, uninitialized state) across the environments you own, achieving repeatable pass/fail results on reruns, including stress runs with randomized seeds across the full regression suite.
• Build DPI-C bridges between SystemVerilog testbenches and C/C++ reference models, enabling bit-accurate checking on complex datapaths.
• Create reusable SystemVerilog packages (randomization utilities, transaction classes, configuration frameworks) adopted across multiple testbenches.
• Reduce testbench compile and elaboration time by 25 percent through disciplined package structure, forward declarations, and lint-clean code.

What you will bring

Must-haves

• 2 to 5 years of verification experience with deep SystemVerilog language expertise beyond UVM boilerplate.
• Mastery of SystemVerilog randomization: constraint solving, randcase, distribution control, and debugging constraint conflicts.
• Strong grasp of interfaces, modports, clocking blocks, and program blocks, including race-avoidance semantics.
• Experience with DPI-C for integrating C/C++ models into SystemVerilog testbenches.
• Proficiency with SVA for both immediate and concurrent assertions in testbench checkers.
• Familiarity with lint tools and coding guidelines that keep large testbench codebases maintainable.
• Debugging skill at the language level: scheduling semantics, event regions, and process control.

Nice-to-haves

• Experience with SystemVerilog multi-threaded testbench patterns (fork/join, mailboxes, semaphores).
• Knowledge of performance profiling tools for simulation optimization.
• Exposure to UVM-SystemC or mixed-language verification environments.
• Familiarity with recent IEEE 1800 language features and their simulator support.