SystemVerilog Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog (advanced language features), UVM, SVA, interfaces/modports, clocking blocks, DPI-C, coverage constructs

About the role

You will be the SystemVerilog language expert on the design verification team of a semiconductor company, the engineer who knows what the simulator actually does with your code. While others write testbenches that happen to work, you write testbenches that are correct by construction: race-free, with intent clear and coverage precise. Designers trust your environments because your SystemVerilog is rigorous, your reviews catch the subtle bugs, and your expertise raises every testbench you touch. You are the engineer teams call when a testbench misbehaves in ways nobody can explain, because you understand what the simulator actually does.

What you will achieve

Deliver race-free, reusable SystemVerilog testbench components (interfaces, clocking blocks, assertion libraries) adopted as team standards across multiple blocks.
Drive assertion quality across the program by writing SVA libraries for common protocols and coaching block owners on property correctness through reviews.
Ship DPI-C integrations that connect high-performance C/C++ reference models to SystemVerilog testbenches with clean, maintainable interfaces and documented ownership.
Cut simulation debug time by eliminating the classic SystemVerilog pitfalls (race conditions, X-optimism, scheduling surprises) from team code through reviews and written guidelines.
Reduce coverage blind spots by applying advanced coverage constructs (covergroups with crosses, transition coverage, assertion coverage) where simple line coverage would lie about completeness.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with deep SystemVerilog fluency well beyond basic UVM usage.
Expert understanding of SystemVerilog scheduling semantics, race avoidance, clocking blocks, and program blocks, applied correctly in practice.
Strong SVA skills: writing, debugging, and reviewing temporal properties for real protocols, not textbook examples.
Experience with DPI-C or similar language interfaces for reference model integration, including performance considerations.
Working UVM knowledge, with informed opinions about where UVM helps and where plain SystemVerilog is the better tool.
Code craftsmanship: your testbench code is readable, reviewed, and built to last across multiple programs.
Mentorship instinct: you enjoy making other engineers better SystemVerilog programmers through reviews and examples.

Nice-to-haves

Familiarity with formal tools and how SVA properties transfer between simulation and formal.
Experience with low-power SystemVerilog constructs or power-aware simulation.
Knowledge of SystemVerilog for design (synthesizable subset) to bridge verification and RTL perspectives.
Exposure to performance profiling of SystemVerilog testbenches and optimization techniques.