Staff ASIC Verification Engineer

ASIC Verification Engineer Staff (L6 equivalent), scope across multiple teams 8-12 years

Other levels: ASIC Verification Engineer Senior ASIC Verification Engineer Principal ASIC Verification Engineer Lead ASIC Verification Engineer Junior ASIC Verification Engineer

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The job description

Tech stack. SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, SVA, formal verification, Python, regression infrastructure, VIP integration

About the role

You will join a fabless semiconductor company where staff verification engineers carry verification ownership across multiple blocks or an entire subsystem, bridging the engineers doing the daily work and the architects defining what gets built. This role owns testbench architecture decisions that affect several teams: reusable VIP, coverage strategy, and the debug infrastructure everyone relies on. You are the person other teams call when a failure crosses block boundaries and nobody can tell whose bug it is, and you bring the system-level understanding to untangle it. Your frameworks get adopted because they work, your signoff judgment holds up under tapeout pressure, and your mentorship turns strong engineers into technical leaders. The subsystem you own will tape out clean because you made verification a team sport instead of a solo effort.

What you will achieve

Architect reusable UVM testbench frameworks adopted by three or more block teams, cutting per-block environment bring-up time by half.
Own verification signoff for a full subsystem, coordinating coverage closure and bug burn-down across multiple engineers and RTL drops.
Resolve cross-block integration failures that stall projects, delivering root-cause analysis within 72 hours on issues spanning two or more teams.
Drive coverage closure on the highest-risk features of the subsystem, reaching signoff targets one full RTL drop ahead of schedule.
Establish debug and triage workflows, including automated failure bucketing, that reduce average time-to-first-debug-answer across the team by 35 percent.

What you will bring

Must-haves

8 to 12 years of ASIC verification experience with ownership of subsystems or multiple complex blocks through tapeout.
Demonstrated ability to design testbench architectures that other engineers successfully reuse and extend.
Advanced UVM and SVA skills, including performance-aware testbenches and complex protocol checking.
Experience integrating third-party VIP and resolving VIP-versus-RTL compliance disputes with vendors.
Strong cross-team debug skills spanning RTL, gate-level, and system-level failures.
History of driving coverage closure across multiple contributors with competing priorities.
Effective technical communication with design leads, architects, and program management.

Nice-to-haves

Formal verification experience for control-logic-heavy blocks.
Exposure to power-aware verification and clock-domain-crossing signoff flows.
Experience with continuous integration practices for RTL verification.
Experience with performance verification and throughput modeling.