SoC Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, full-chip testbenches, C/C++ firmware, UPF low-power verification, HW/SW co-verification, Synopsys VCS, Palladium or Zebu basics

About the role

You will verify complete systems-on-chip at a fabless semiconductor company, working at the level where processors, interconnects, memory subsystems, and peripherals all have to work together. SoC verification is integration verification: boot flows, power sequences, interrupt routing, and the hardware-software boundary that block-level testing never exercises. Your testbench proves the chip works as a system, not just as a collection of verified blocks. You will write the firmware-driven scenarios that boot the chip in simulation, chase the integration bugs that hide in the seams between IP blocks, and verify the power and clocking behavior that only exists at full-chip scope. When the chip powers up in the lab and boots on the first try, your verification is a big part of the reason.

What you will achieve

Build full-chip UVM testbenches with processor-driven C tests that boot firmware and exercise end-to-end data paths across the SoC.
Verify power intent at the SoC level with UPF-driven simulation, covering power-up sequences, domain shutdown, and retention across all defined power states.
Drive SoC-level functional coverage closure, including system scenarios such as concurrent peripheral traffic, interrupt storms, and error injection.
Debug integration failures spanning multiple IP blocks, delivering root-cause analysis that distinguishes interconnect, firmware, and block-level issues.
Reduce full-chip regression runtime by 30 percent through smart test selection and checkpoint-restore techniques for long boot sequences.

What you will bring

Must-haves

2 to 5 years of SoC or subsystem-level verification experience with SystemVerilog and UVM.
Experience with HW/SW co-verification: writing or integrating C firmware tests that run on embedded processors in simulation.
Understanding of SoC architecture elements: interconnects, memory maps, interrupt controllers, clock and reset networks.
Low-power verification experience with UPF, including power-aware simulation and state-transition checking.
Strong system-level debug skills across waveforms, processor traces, and transaction-level logs.
Familiarity with AMBA interconnect protocols (AXI, ACE) and standard peripheral interfaces.
Ability to read architecture specifications and translate system use cases into verification scenarios.

Nice-to-haves

Exposure to emulation platforms for accelerating SoC-level software validation.
Experience with virtual prototypes or hybrid simulation environments.
Knowledge of security verification concepts such as secure boot flows.
Familiarity with firmware development in C for bare-metal test content.