SoC Mixed Signal Design Engineer

About the role

You will own mixed-signal integration at the SoC level for a fabless semiconductor company taping out complex chips with dozens of analog blocks. The team sits between the analog designers and the digital top-level group, responsible for the interfaces, power plans, and verification that make the whole chip come up together. This role matters because most chip failures are integration failures, and you are the engineer whose job is to prevent them. You will also own the top-level AMS verification plan that proves analog and digital blocks behave together, catching the interface bugs that block-level simulation always misses.

What you will achieve

• Deliver clean SoC tapeouts where every analog block integrates without interface surprises: pad ring, power domains, clock distribution, and reset sequencing all verified at the top level before tapeout.
• Reduce top-level AMS simulation failures by building and maintaining real-number models for every analog IP, so full-chip co-simulation runs in hours instead of days and catches real bugs.
• Own the mixed-signal verification methodology: define the AMS regression suite (power-up sequences, mode transitions, PVT corners) that runs on every top-level database drop.
• Cut substrate and supply noise issues by defining the top-level isolation strategy: guard rings, separate supplies, deep n-well usage, and sensitive-signal routing rules enforced across the floorplan.
• Drive chip-level bring-up efficiency by writing the analog portions of the bring-up plan and debugging integration issues (PLL lock failures, reference settling, LDO stability under load steps) in the lab.

What you will bring

Must-haves

• 2-5 years in analog/mixed-signal design or integration with at least one SoC tapeout where you owned top-level analog integration or verification.
• Fluency in SystemVerilog real-number modeling and AMS co-simulation (AMS Designer or equivalent) for full-chip verification.
• Understanding of top-level analog concerns: power domain planning, ESD and pad ring design, clock distribution, and substrate isolation strategy.
• Experience writing or maintaining AMS regression suites: power-up sequences, mode transitions, and interface checks across PVT corners.
• Ability to debug chip-level analog issues in the lab and trace them to block-level or integration root causes.
• Clear documentation habits: interface specs, integration checklists, and bring-up plans that other teams can execute.

Nice-to-haves

• Familiarity with UVM and mixed-signal assertion methodology.
• Experience with multi-die or chiplet integration and die-to-die analog interfaces.
• Knowledge of IR drop and EM analysis at the full-chip level.