SoC Firmware Engineer

Firmware Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Boot firmware architecture, ARM Trusted Firmware (ATF), secure boot chains, device tree configuration, SoC initialization (clock trees, DDR controllers, interconnects), power management firmware (DVFS, suspend/resume), JTAG and trace debugging, pre-silicon virtual platforms

About the role

You will write the very first code that ever executes on new systems-on-chip, working in the rarefied space where your firmware is the difference between a dead piece of silicon and a booting platform. SoC firmware engineers own the boot sequence completely: ROM extensions, ARM Trusted Firmware, DDR controller initialization, and the precise handoff to operating systems. You will begin on pre-silicon models and FPGA prototypes, then move to first silicon where you will debug with minimal visibility and maximum patience. It is slow, methodical, high-stakes engineering: entire product program schedules depend on your bring-up progress, and when the silicon is brand new there is simply no one to escalate to.

What you will achieve

Develop complete boot firmware including secondary program loaders, ARM Trusted Firmware integration, and board initialization configuring clocks, DDR memory, and interconnects correctly
Deliver production secure boot implementations with an unbroken, verified chain of trust extending from immutable ROM through the operating system
Bring up new silicon revisions successfully: diagnosing initialization failures using JTAG debuggers, hardware trace, and meticulous register-level analysis
Write power management firmware covering DVFS policies, suspend and resume sequences, and power domain control, all validated on real hardware
Create comprehensive device trees, platform bring-up documentation, and integration guides enabling OS, driver, and product teams to build confidently on your work

What you will bring

Must-haves

2 to 5 years in boot firmware development, SoC enablement, or low-level embedded software with direct silicon bring-up experience
Thorough understanding of ARM boot architecture: ROM code responsibilities, trusted firmware stages (BL1/BL2/BL31), U-Boot integration, and device tree handoff mechanics
Hands-on experience with DDR controller initialization and systematic, patient debugging of memory training and calibration failures
Knowledge of secure boot engineering: cryptographic key provisioning, signature verification flows, rollback protection, and one-time-programmable fuse procedures
Ability to debug effectively with JTAG on unproven first silicon: methodical approach, creative use of extremely limited visibility, and persistence
Familiarity with the clock, reset, and power domain architectures of modern complex SoCs and their interdependencies
BS in Electrical or Computer Engineering

Nice-to-haves

Experience with RISC-V boot architectures: OpenSBI, U-Boot SPL, and the RISC-V privileged specification
Familiarity with pre-silicon development using virtual platforms, FPGA prototypes, or hardware emulation systems
Knowledge of firmware TPM implementations, measured boot architectures, or DICE device identity standards
Experience managing silicon errata: tracking, workaround implementation, and verification across stepping revisions