SoC Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, SoC integration testbenches, C-based firmware test, AMBA protocols (AXI/APB/AHB), memory subsystem verification, boot flow

About the role

You will verify complete systems-on-chip at a fabless semiconductor company, where the hardest bugs live at the seams: between the CPU and its interconnect, between DMA engines and memory, between firmware and hardware. You will work with designers across every IP block to prove the integrated system boots, performs, and behaves under real software load. Your signoff is the last gate before a multi-million-dollar tapeout, and the program treats it that way.

What you will achieve

Deliver SoC-level verification environments that boot production firmware on the integrated netlist, covering reset, clocking, and power sequencing end to end.
Drive system-level use-case coverage (boot, suspend/resume, high-bandwidth DMA, interrupt storms) to the targets defined in the verification plan, with gaps escalated early.
Ship integration bug finds that block owners missed, measured by a documented pipeline of cross-block issues driven to RTL closure at each milestone.
Cut SoC regression turnaround by building targeted, fast-running integration suites that catch interface breakage within hours of an IP drop.
Reduce tapeout risk by co-validating the memory map, address decoding, and bus fabric performance against the architecture specification together with designers.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with exposure to full-chip or subsystem integration beyond pure block-level work.
Solid SystemVerilog/UVM skills plus the ability to write and debug C tests that run on embedded processors in simulation.
Understanding of AMBA protocols and SoC fabric concepts: arbitration, QoS, address mapping, and coherency basics.
Experience debugging failures that span hardware and firmware, working jointly with designers and software engineers to reach root cause.
Knowledge of boot sequences, reset domains, and clock generation as they interact at the SoC level.
Patience and method: SoC debug is slow and layered, and you keep investigations organized when the failure crosses five blocks.
Clear escalation judgment: you know when an integration issue is a testbench artifact and when it threatens the tapeout.

Nice-to-haves

Experience with performance verification or bus fabric throughput analysis.
Familiarity with emulation for software-driven SoC scenarios.
Exposure to low-power SoC verification (power intent, isolation, retention).
Knowledge of security or safety features at the SoC level (secure boot, firewalls).