SoC CPU Integration Engineer

About the role

You will integrate CPU subsystems into SoCs at a semiconductor company, assembling processor clusters, system interconnects, memory controllers, and supporting IP into a coherent working chip. Integration engineers own the demanding phase where independently designed blocks become a unified system: they connect interfaces correctly, resolve the inevitable integration issues, verify subsystem-level behavior, and ensure the assembled SoC faithfully implements its architectural intent. Your work determines whether a collection of excellent blocks becomes an excellent product.

What you will achieve

• Integrate CPU clusters with system fabrics, memory subsystems, interrupt controllers, and peripherals, connecting interfaces correctly and resolving protocol, data width, clocking, and reset mismatches.
• Own subsystem-level verification including integration testbenches, static connectivity checking, and system-level use-case validation across operating modes.
• Resolve integration issues systematically, tracing problems across block boundaries to root causes in design bugs, configuration errors, or interface misunderstandings.
• Manage design configuration, version control, and build flows for the subsystem, ensuring reproducible integration drops and clean handoffs between contributing teams.
• Support full-chip verification, emulation, and FPGA prototyping efforts, enabling system-level testing and early software development on the integrated CPU subsystem.
• Document the integrated subsystem thoroughly including memory maps, interface specifications, clocking and reset architecture, and integration notes for software, validation, and product teams.

What you will bring

Must-haves

• 2 to 5 years of experience in SoC integration, subsystem design, or complex ASIC implementation with tapeout exposure.
• Strong understanding of SoC architecture fundamentals: system interconnects, memory maps, clocking and reset networks, and power domain partitioning.
• SystemVerilog skills for integration logic, glue logic, configuration registers, and testbench development.
• Experience with industry-standard interface protocols such as AXI, ACE, or CHI and the discipline to connect them correctly across clock and power domains.
• Systematic debug skills for cross-block issues with multiple plausible root causes and incomplete information.
• Familiarity with version control, configuration management, and build automation for large hardware projects.
• Communication and coordination skills for working across multiple block teams with different schedules and priorities.

Nice-to-haves

• Experience with CPU subsystem specifics including coherency domain integration, debug and trace infrastructure, and boot flows.
• Knowledge of emulation or FPGA prototyping platforms for system validation.
• Familiarity with SoC-level power management integration and firmware interfaces.
• Exposure to security IP integration including root of trust and secure boot.