SoC CPU Architect

About the role

You will architect the CPU subsystem within a larger SoC at a semiconductor company, defining how clusters of processors integrate with memory, accelerators, IO, and system infrastructure. SoC CPU architects own the boundary where the CPU meets everything else: the cluster-level cache hierarchy, the coherency domain, the interfaces to the fabric, the power and clock architecture, and the debug and security infrastructure. Your work determines whether a collection of excellent blocks becomes an excellent system.

What you will achieve

• Define the CPU subsystem architecture for an SoC program including core count and configuration, cluster-level caches, coherency scope, and interfaces to the system fabric.
• Architect the subsystem-level power and clock management including voltage domains, power islands, retention strategies, and the sequencing that brings the subsystem up and down reliably.
• Specify the debug, trace, and performance monitoring infrastructure for the CPU subsystem, ensuring software teams can develop, optimize, and diagnose on the final product.
• Drive the integration of the CPU subsystem with accelerators, memory controllers, and IO, resolving interface, coherency, and quality-of-service questions with system-level data.
• Model subsystem-level performance and power across the SoC workload set, validating that the CPU complex meets its targets in the context of the full system rather than in isolation.
• Support integration, verification, and silicon bring-up of the CPU subsystem, resolving cross-block issues and protecting the program's system-level commitments.

What you will bring

Must-haves

• 5 to 8 years of experience in SoC architecture, CPU subsystem design, or system-level integration with shipped products.
• Strong understanding of multi-core coherency, cluster architectures, system fabrics, and memory subsystem integration.
• Experience with SoC power management architectures including power domains, sequencing, and firmware interfaces.
• Knowledge of debug and trace architectures and their importance to software enablement and post-silicon debug.
• Performance modeling skills at the subsystem and system level with attention to realistic SoC traffic and contention.
• Ability to specify interfaces and integration requirements consumed by multiple block-level teams.
• Systems thinking with the communication skills to align diverse teams behind subsystem-level decisions.

Nice-to-haves

• Experience with security architecture including root of trust, secure boot, and memory encryption at the subsystem level.
• Familiarity with automotive, mobile, or datacenter SoC requirements and their architectural implications.
• Background in chiplet-based SoC architectures.