SerDes Mixed Signal Design Engineer

About the role

You will design the mixed-signal circuits inside high-speed SerDes links at a fabless semiconductor company shipping connectivity IP. The team owns the transmitter, receiver front end, CDR, and equalization that must close the link across lossy channels at 56 Gbps and beyond. This role matters because SerDes is the product's most visible spec, and your jitter, equalization, and power numbers decide whether the link works in a real system. You will work with channel and packaging engineers on the full link budget, since SerDes margin is a system property your circuits must deliver into.

What you will achieve

• Ship SerDes mixed-signal blocks (TX driver, RX CTLE/DFE, CDR, or phase interpolator) that close the link with positive margin on measured BER across the target channel loss.
• Drive receiver jitter tolerance by designing CDR loops and phase interpolators that track the required jitter mask with margin, verified in both simulation and lab.
• Reduce power per Gbps through circuit technique: deliver your blocks at or below the link power budget while holding performance, improving on the prior generation.
• Own statistical link modeling in MATLAB: channel, package, and crosstalk models that predict link margin within 1 dB of lab measurement before tapeout.
• Cut lab characterization time by building automated test setups: BERT-based bathtub curves, jitter tolerance sweeps, and equalization adaptation verification scripted in Python.

What you will bring

Must-haves

• 2-5 years designing SerDes or high-speed wireline circuits (TX, RX, CDR, equalization, or phase interpolators) with tapeout and lab-measured link results.
• Deep understanding of equalization: CTLE, DFE, FFE, and how they trade against channel loss and crosstalk.
• Fluency in CDR architectures (bang-bang, linear, baud-rate) and jitter analysis: jitter generation, tolerance, and transfer.
• Experience with PAM4 signaling: linearity requirements, SNR budgeting, and Gray coding implications for the analog front end.
• Statistical link modeling skills in MATLAB or Python: building channel models and predicting BER margin before silicon.
• Lab skills with BERTs, sampling scopes, and jitter analysis for link characterization.

Nice-to-haves

• Experience with 112 Gbps or higher data rates, or with DSP-based SerDes architectures.
• Knowledge of standards (PCIe, Ethernet, USB, or OIF) and their SerDes compliance requirements.
• Familiarity with forward error correction and its interaction with raw BER targets.