SerDes IC Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SerDes architecture, equalization (CTLE/DFE/FFE), CDR, PAM4/NRZ, jitter budgeting, link training, Cadence Virtuoso, Spectre, IBIS-AMI modeling

About the role

You will join a connectivity IP company designing SerDes macros licensed into customer SoCs across data center, networking, and consumer markets. The team owns the complete serializer-deserializer: TX, RX, clocking, and the digital adaptation that makes links robust. This role matters because your macro's power, area, and BER determine whether customers choose this IP over competitors, and link failures in the field are the costliest kind. Standards evolve continuously, and each new speed grade is a fresh chance to win or lose major sockets. Customers integrate these macros into chips you will recognize, which makes the work highly visible. You will also define the link-training and adaptation firmware interface, so the digital team can implement calibration algorithms that keep BER low across voltage and temperature corners.

What you will achieve

Deliver SerDes lanes that achieve target BER (1e-12 or better) across specified channels with margin demonstrated in both simulation and silicon
Design adaptive equalization that converges reliably across channel variation, eliminating manual tuning in customer bring-up
Cut lane power and area generation over generation while holding or improving jitter tolerance and transfer performance
Build IBIS-AMI and statistical models that let customers sign off their channels before your silicon exists
Drive compliance testing against standards (PCIe, Ethernet, USB4) so customer products pass certification on first attempt
Support customer integration with clear documentation, training, and debug of link issues in their systems
Track standards-body developments and keep the IP roadmap ready for when new electrical specs are ratified

What you will bring

Must-haves

2-5 years designing SerDes or high-speed link circuits with at least one shipped product or licensed IP
Strong grasp of link analysis: channel loss, reflections, crosstalk, jitter decomposition, and BER estimation
Design experience across the SerDes signal path: TX drivers, RX front ends, equalizers, CDR, and clock distribution
Proficiency in Cadence Virtuoso and Spectre; familiarity with statistical and time-domain link simulation tools
Understanding of adaptive algorithms: LMS, sign-sign, and eye-monitor-based adaptation for equalizer training
Experience with at least one industry standard's electrical specification and compliance methodology
B.S. or M.S. in Electrical Engineering with a high-speed mixed-signal focus

Nice-to-haves

PAM4 signaling and FEC-aware link design experience
Familiarity with DSP-based SerDes architectures and firmware interaction
Prior customer-facing IP support or application engineering work