SerDes Analog Design Engineer

Analog Design Engineer Senior (L5 equivalent) 5-8 years

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Texas Instruments

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The job description

Tech stack. SerDes design, wireline transceivers, adaptive equalization, CDR architectures, Cadence Virtuoso, Spectre, link modeling, jitter analysis, multi-standard compliance

About the role

You will design serializer-deserializer circuits at a semiconductor company, building the complete high-speed wireline transceivers that carry data between chips, boards, and systems. SerDes designers own the full link: transmitters with pre-emphasis, receivers with adaptive equalization, clock and data recovery, and the calibration engines that optimize everything automatically. You will design these blocks, model end-to-end link performance, ensure compliance with standards like PCIe and Ethernet, and validate bit error rates on silicon. You will also drive post-silicon link tuning with customers, using IBIS-AMI models and lab measurements to close the last decibels of margin on real channels.

What you will achieve

Design complete SerDes transceivers including TX drivers with FFE, RX front ends with CTLE and DFE, and CDR circuits meeting multi-gigabit performance targets.
Implement adaptive equalization and calibration algorithms in collaboration with digital designers, ensuring robust link operation across channel variation without manual tuning.
Model end-to-end link performance using channel S-parameters, statistical eye analysis, and jitter budgeting to prove compliance margins before tapeout.
Design clocking architectures for SerDes including PLLs, phase interpolators, and clock distribution with the jitter performance multi-gigabit links demand.
Ensure standards compliance through rigorous specification analysis, compliance test planning, and pre-silicon verification against PCIe, Ethernet, USB, or other target standards.
Validate SerDes performance on silicon with BERT scans, jitter tolerance testing, and compliance measurements, debugging link issues systematically from channel through equalization to clock recovery.

What you will bring

Must-haves

5 to 8 years of experience in SerDes, wireline transceiver, or high-speed IO design with shipped products.
Deep understanding of wireline link fundamentals: channel impairments, equalization theory, CDR architectures, and jitter.
Strong analog circuit design skills for broadband front ends, comparators, and mixed-signal feedback loops.
Experience with link modeling tools and methodologies including statistical simulation and channel analysis.
Knowledge of industry standards such as PCIe, Ethernet, USB, or OIF specifications and their electrical requirements.
Bench validation expertise for high-speed links including BERTs, real-time oscilloscopes, and compliance test setups.
Ability to collaborate across analog, digital, firmware, and system teams on link optimization.

Nice-to-haves

Experience with PAM4 SerDes design and its unique challenges.
Familiarity with 112G and 224G signaling generations.
Knowledge of co-packaged optics or optical SerDes interfaces.
Background in backplane or long-reach channel design.