Senior Mixed Signal Design Engineer

About the role

You will be the technical anchor of the analog group at a fabless semiconductor company building high-performance mixed-signal SoCs. The team owns the analog front ends and signal chains that differentiate the product line, and senior designers set the standard for what "tapeout ready" means. This role matters because your blocks will define the datasheet specs customers buy against, and your judgment will decide when a design is good enough to freeze and when it needs one more iteration.

What you will achieve

• Deliver two or more complex mixed-signal blocks per year (e.g. multi-bit pipeline ADC, fractional-N PLL, high-speed DAC) with first-silicon success and datasheet-level specs met without metal spins.
• Lead block-level architecture trade studies that pick the right topology for the spec (SAR vs pipeline vs delta-sigma, LC vs ring VCO), documented with measured-versus-modeled comparisons from prior silicon.
• Drive a 20-30% reduction in block power or area versus the prior generation by applying circuit techniques you have proven in silicon (dynamic biasing, supply scaling, calibration).
• Own the analog sign-off checklist for your blocks: parasitic-extracted corners, Monte Carlo yield analysis, EM/IR checks, ESD and latch-up review, and reliability sign-off completed before every tapeout.
• Mentor junior designers through design reviews, teaching them to defend architectural choices with data and to spot the second-order effects (kickback, charge injection, reference bounce) that break first silicon.

What you will bring

Must-haves

• 5-8 years of analog/mixed-signal design in CMOS with multiple successful tapeouts and first-silicon bring-up on your record.
• Deep expertise in at least one domain: data converters, PLLs/clocking, high-speed I/O, power management, or precision analog.
• Proven ability to run full sign-off flows independently: extracted-view corners, statistical yield analysis, EM/IR, ESD/latch-up, and reliability checks.
• Strong lab debug skills: root-causing silicon issues to circuit or layout mechanisms and driving fixes into the next revision.
• Experience mentoring or technically reviewing the work of less experienced designers.
• Solid grasp of noise, mismatch, distortion, and bandwidth fundamentals, applied at the transistor level rather than from textbooks.

Nice-to-haves

• Tapeout experience in finFET nodes (16nm, 7nm, or below) with layout-dependent-effect awareness.
• Knowledge of digital calibration or background calibration techniques for analog blocks.
• Familiarity with AMS top-level verification methodology and real-number modeling.