Senior CPU Architect

About the role

You will join a processor development team as a senior individual contributor shaping the microarchitecture of next-generation CPUs destined for high-volume production. This team turns product requirements and market analysis into shipping silicon, and senior architects carry the most technically demanding subsystems from initial concept through tapeout and post-silicon validation. You will set the technical direction for your area, mentor junior architects deliberately, and be personally accountable for the performance claims the product is marketed and sold on.

What you will achieve

• Own the end-to-end microarchitecture of a major CPU subsystem from early-stage modeling and detailed specification through implementation support, verification closure, and post-silicon performance validation.
• Deliver a performance projection model for your subsystem that lands within 3 percent of measured silicon across the full benchmark suite, earning the organization's trust in your methodology.
• Lead the tradeoff studies that resolve the hardest performance versus power versus area conflicts in the program, earning formal sign-off from architecture leadership with thorough, data-driven recommendations.
• Mentor two or more junior architects actively, reviewing their models and specifications in detail and raising the bar on analytical rigor and documentation quality across the team.
• Drive at least one significant microarchitectural innovation per program, such as a novel prefetcher, scheduler policy, or power management scheme, from initial concept through modeling, specification, and shipping silicon.
• Represent the architecture team in cross-functional reviews with design, verification, physical design, and software organizations, communicating complex decisions clearly and building alignment.

What you will bring

Must-haves

• 5 to 8 years of experience in CPU architecture, performance modeling, or high-performance CPU design with shipped products.
• Deep knowledge of out-of-order execution, speculation and recovery mechanisms, memory subsystem design, and their interactions.
• Track record of owning a significant subsystem through at least one complete tapeout cycle including post-silicon correlation and debug.
• Strong quantitative skills: you build credible models, measure carefully, characterize uncertainty, and decide with data rather than intuition or authority.
• Fluency in at least one major ISA along with a working understanding of its software ecosystem implications for hardware decisions.
• Experience writing architecture specifications consumed by large, distributed design teams with minimal ambiguity.
• Ability to defend technical positions to senior leadership with evidence, and to change your position gracefully when the evidence demands it.

Nice-to-haves

• Product experience across datacenter, client, mobile, or embedded SoC generations.
• Knowledge of advanced power management techniques such as DVFS, adaptive voltage scaling, power gating, and workload-aware policies.
• Published work, patents, or conference presentations in computer architecture.