Semiconductor Test Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. ATE (Advantest/Teradyne), wafer probe, final test, test program development, handlers/probers, STDF, gauge R&R, DFT

About the role

A semiconductor manufacturer needs a test engineer to own wafer probe and final test for production devices, the last technical gate before product reaches customers. You will develop and sustain test programs, improve test coverage while cutting test time, and keep test escapes at zero even as volumes scale. Your work determines whether the fab's good die actually ship as good product, and a single escape can cost more than a year of test engineering, so rigor here is non-negotiable. The test engineer also owns the test-time reduction roadmap, driving handler and prober optimizations that cut cost per die while holding coverage and zero-escape quality.

What you will achieve

Ship qualified test programs that achieve greater than 99.5 percent fault coverage with zero test escapes to the field, validated through gauge studies and correlation across sites.
Reduce test time per device by 15 percent through multi-site optimization, pattern streamlining, and removal of redundant measurements that add no coverage.
Drive probe-card and hardware correlation so first-silicon test results match within 2 percent across sites, eliminating site-to-site yield deltas that mask real issues, and enabling true apples-to-apples comparisons of process changes.
Own tester utilization on your platforms, sustaining above 90 percent through preventive maintenance scheduling and rapid recovery from tester faults.
Cut test-related yield loss by diagnosing bin fallout patterns and feeding fixes back to design and process teams with data that pinpoints the mechanism, and recommended containment actions for suspect material.

What you will bring

Must-haves

BS or MS in electrical engineering or computer engineering with solid digital and analog fundamentals.
2 to 5 years developing or sustaining ATE test programs on platforms such as Advantest 93K or Teradyne UltraFlex.
Experience with wafer probe and final test flows, including handlers, probers, and probe-card management.
Proficiency in C/C++ or similar languages for test program development and debug.
Understanding of DFT concepts such as scan, BIST, and boundary scan, and how they translate into test patterns.
Strong debug skills using shmoo plots, datalogs, and failure analysis to resolve low-yield or no-yield situations.

Nice-to-haves

Experience with mixed-signal or RF test techniques, including calibration and de-embedding.
Knowledge of STDF data formats and test data analytics for yield and quality monitoring.
Familiarity with burn-in or system-level test flows for high-reliability products.