Semiconductor Packaging Engineer

Semiconductor Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. flip-chip, wirebond, substrates (organic/ceramic), leadframe, mold compound, underfill, package co-design, warpage metrology, JEDEC qualification

About the role

An OSAT needs a packaging engineer to develop and qualify assembly processes for advanced packages, where electrical performance, thermal behavior, and mechanical reliability all have to be designed in together. You will own package design rules, assembly flows, and qualification plans from substrate selection through final test handoff, working with design teams long before tooling is cut. Your work determines whether great silicon becomes a reliable product, because the best die in the world is worthless if the package fails in the field.

What you will achieve

Deliver qualified package flows that pass JEDEC reliability standards on first attempt for 80 percent of new packages, through rigorous design-rule checks and pre-qualification risk assessments.
Reduce assembly yield loss by 2 points through process window studies on die attach, wirebond, and molding, with optimized parameters locked into controlled production recipes.
Drive package co-design with design teams so electrical, thermal, and mechanical requirements are all met before tooling starts, avoiding late redesigns that slip schedules by months.
Cut package development cycle time by 20 percent with standardized qualification templates, parallel test plans, and early engagement with substrate and material suppliers.
Own failure investigations on package-related customer returns, closing them with verified corrective actions and updated design rules that prevent recurrence, and sharing the learning across programs so it compounds.

What you will bring

Must-haves

BS or MS in mechanical engineering, materials science, electrical engineering, or physics.
2 to 5 years in semiconductor packaging, assembly process engineering, or package design with production package releases.
Hands-on knowledge of flip-chip, wirebond, or QFN/BGA package families, including their process flows and failure modes.
Experience with substrate design rules and supplier interactions, from stack-up definition through qualification.
Understanding of package reliability stresses including temperature cycling, HAST, and drop test, and how design choices affect results.
Ability to run DOE and analyze results for assembly process optimization, with statistical justification for parameter changes.

Nice-to-haves

Experience with 2.5D/3D packaging, chiplets, or fan-out wafer-level packaging for high-performance applications.
Thermal or mechanical simulation experience using ANSYS, Abaqus, or similar tools.
Familiarity with warpage measurement techniques such as shadow moire and their use in process control.