Semiconductor Device Engineer

About the role

A fabless chip company with captive fab partners needs a device engineer to own transistor and passive-device performance from design kit through silicon, the technical foundation every circuit designer builds on. You will model, measure, and tune devices so that PDK models match silicon across corners, and you will investigate every parametric anomaly until the physics is understood. Your work is the link between process capability and circuit performance, and designers can only be as aggressive as your models allow them to be.

What you will achieve

• Deliver compact models for new device flavors with model-to-silicon error below 5 percent across process corners, validated against measured I-V and C-V data from multiple lots.
• Drive device-level root-cause analysis on parametric outliers, cutting characterization cycle time by 30 percent through standardized measurement plans and automated data pipelines.
• Own I-V and C-V measurement plans for technology qualification, covering temperature and voltage corners with enough statistical depth to support model extraction.
• Reduce layout-dependent-effect discrepancies by calibrating TCAD decks against split-lot silicon data, so designers see accurate stress and proximity effects in simulation.
• Ship PDK device documentation updates on schedule so design teams hit tape-out milestones without rework caused by late or inaccurate device data, and with full confidence in corner coverage.

What you will bring

Must-haves

• BS or MS in electrical engineering, physics, or applied physics, with device-physics coursework required and semiconductor device theory at the core of your training.
• 2 to 5 years in device engineering, device modeling, or technology development with direct silicon measurement experience.
• Hands-on TCAD experience (Sentaurus, Silvaco, or equivalent) for device simulation, including structure definition and physics model selection.
• Proficiency with I-V and C-V measurement setups and parameter analyzers, from probe-station operation to data interpretation.
• Understanding of CMOS device physics including short-channel effects, quantum effects, and reliability mechanisms like BTI and hot carriers.
• Ability to communicate model limitations and trade-offs to circuit designers in terms they can act on.

Nice-to-haves

• Experience with BSIM or PSP compact-model extraction flows and parameter optimization.
• Knowledge of ESD devices or high-voltage device design and their modeling quirks.
• Familiarity with cryogenic or high-temperature device characterization for specialty applications.