RTL Design Engineer (CPU)

About the role

You will write production RTL for CPUs at a semiconductor company, implementing the register-transfer-level logic that synthesis turns into the processor's gates. RTL design engineers are the builders of the chip: their code becomes the product, and its quality determines functionality, timing, power, and area. You will implement blocks from specifications, verify them rigorously, iterate with physical design until timing closes, and support the design through silicon, developing deep expertise in the craft of hardware description and the discipline of quality-driven delivery.

What you will achieve

• Write clean, synthesizable SystemVerilog RTL for CPU blocks according to microarchitecture specifications, with coding style that is readable, maintainable, and genuinely review-friendly.
• Verify your RTL with block-level testbenches to the coverage targets required, finding and fixing bugs through systematic testing before they reach integration and become expensive.
• Iterate on timing with synthesis and physical design feedback, restructuring logic, balancing pipelines, and adding stages where analysis shows they are needed rather than hoping constraints will be met.
• Follow the team's RTL methodology rigorously including naming conventions, assertion usage, clocking disciplines, and documentation standards, treating consistency as a feature.
• Participate actively in code reviews both as author and reviewer, giving detailed, constructive technical feedback and receiving it gracefully, improving everyone's RTL including your own.
• Support post-silicon debug of your blocks, using your intimate knowledge of the implementation to diagnose issues rapidly and propose fixes or workarounds under schedule pressure.

What you will bring

Must-haves

• 2 to 5 years of experience writing production RTL for processors, SoCs, or ASICs with tapeout exposure.
• Strong SystemVerilog skills with deep knowledge of synthesizable constructs and their actual hardware implications.
• Understanding of what makes RTL timing-friendly: logic depth awareness, register placement intuition, pipeline thinking, and restraint with complex combinational paths.
• Experience with functional verification at the block level and systematic debug skills using waveforms and assertions.
• Familiarity with synthesis, timing constraints, and the fundamentals of static timing analysis.
• Discipline for following methodology and documentation standards consistently even under schedule pressure.
• Responsiveness and ownership in supporting integration, verification, and debug needs from neighboring teams.

Nice-to-haves

• Experience with parameterized, reusable RTL design and IP-quality coding practices.
• Knowledge of low-power RTL techniques and power intent flows.
• Exposure to emulation or FPGA prototyping of RTL designs.
• Familiarity with formal equivalence checking between RTL and netlists.