R&D Mixed Signal Design Engineer

About the role

You will do research-grade mixed-signal design at a semiconductor R&D organization that prototypes the circuits of two generations from now. The team tapes out test chips to prove new architectures, publishes results, and transfers the winners into product development. This role matters because the company's future product differentiation is invented in your lab, and your prototypes decide which ideas survive contact with silicon.

What you will achieve

• Tape out one to two research test chips per year proving a novel mixed-signal architecture (new converter topology, calibration scheme, or ultra-low-power technique) with measured results that beat the published state of the art.
• Drive idea-to-silicon velocity: take a concept from MATLAB modeling through test-chip design, tapeout, and lab measurement in under 12 months, with honest reporting of what worked and what did not.
• Reduce productization risk by writing transfer packages for successful prototypes: architecture documentation, measured-versus-modeled analysis, and a clear statement of what a product team must change to adopt the technique.
• Build the organization's research reputation by publishing at least one paper or patent per year from your measured results, with reproducible data and clear comparisons to prior art.
• Cut wasted research cycles by killing ideas early: define go/no-go metrics up front and stop projects that miss them, redirecting effort to the most promising directions.

What you will bring

Must-haves

• 4-7 years of analog/mixed-signal design with at least one research tapeout (test chip, MPW, or university silicon) and measured results you can present.
• Proven ability to originate circuit ideas: not just implementing specs, but proposing architectures and defending them with analysis and modeling.
• Strong MATLAB/Python modeling skills for architecture exploration before committing to silicon.
• Full test-chip flow experience: pad-limited floorplanning, ESD for test structures, DFT for analog, and bringing up bare dies in the lab.
• Honest experimental discipline: designing measurements that can falsify your hypothesis, not just confirm it.
• Clear technical writing: papers, invention disclosures, or internal research reports that others can build on.

Nice-to-haves

• Publications at ISSCC, VLSI Symposium, JSSC, or CICC.
• Experience transferring a research prototype into a production product.
• Familiarity with emerging devices or processes (FD-SOI, GaN, advanced packaging) and their analog implications.