R&D ASIC Verification Engineer

About the role

You will research and productize the next generation of verification techniques at a semiconductor company investing in how verification gets done, not just in what gets verified. This R&D role sits between research and production: you prototype new approaches such as ML-assisted coverage closure, intelligent stimulus generation, and automated bug hunting, then harden the ones that work into flows the project teams adopt. You will run experiments on real production RTL, measure results with rigor, and kill ideas that do not survive contact with reality. Your success is measured by techniques that move from your lab into tapeout-critical use, changing how the company's engineers verify. This is where verification methodology gets invented rather than inherited.

What you will achieve

• Prototype ML-assisted verification techniques (coverage prediction, failure triage, stimulus optimization) and demonstrate measurable gains on production designs.
• Productize at least one research prototype per year into a supported flow adopted by project verification teams.
• Reduce coverage closure effort by 30 percent on pilot blocks through intelligent test selection or automated coverage analysis, and publish the methodology so project teams can apply it without your direct involvement.
• Publish internal technical reports and present findings that influence the company's verification technology roadmap.
• Evaluate emerging EDA capabilities and academic research, translating the promising ones into practical experiments on real RTL.

What you will bring

Must-haves

• 4 to 7 years of ASIC verification experience with a strong record on production tapeouts.
• Deep UVM and SystemVerilog expertise sufficient to prototype new techniques on real testbenches.
• Research mindset: formulating hypotheses, designing experiments, and measuring results with statistical rigor.
• Python and data-analysis skills for building ML or analytics prototypes on verification data.
• Familiarity with emerging verification approaches: portable stimulus, ML-driven verification, or formal-method advances.
• Ability to write production-quality code when a prototype graduates to a supported flow.
• Clear communication of research results to both engineering teams and technical leadership.

Nice-to-haves

• Graduate-level coursework or publications in machine learning, formal methods, or EDA.
• Experience contributing to open-source verification tools or methodologies.
• Knowledge of reinforcement learning or Bayesian optimization applied to test generation.
• Familiarity with large language models applied to RTL or testbench generation.