Processor Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, ISA-level checking, riscv-formal or equivalent, random instruction generators, pipeline verification, Synopsys VCS

About the role

You will verify processor cores at a semiconductor company designing CPUs for datacenter, edge, or embedded products. Processor verification is ISA verification: proving that every instruction executes correctly, that exceptions and interrupts behave precisely, and that the pipeline handles hazards, speculation, and memory ordering exactly as the architecture demands. Your random instruction streams and ISA-level checkers are what stand between a subtle pipeline bug and a chip that miscomputes. You will develop the deep microarchitectural intuition that lets you aim stimulus at the pipeline's weakest points, build the reference models that define correct behavior, and debug failures that span fetch, decode, execute, and memory. A processor that executes billions of instructions correctly does so because your verification left no instruction untested.

What you will achieve

Verify ISA compliance across the full instruction set, closing functional coverage on every instruction, addressing mode, and exception path.
Build random instruction generators with architectural checkers that compare DUT behavior against an ISA simulator on millions of instruction sequences.
Prove correct handling of pipeline hazards, branch misprediction recovery, and precise exception delivery under randomized stress.
Verify memory consistency and ordering rules, catching subtle load-store and atomic-operation bugs before they reach silicon, and build litmus-style tests that target the weakest ordering guarantees of the memory model.
Drive debug on processor failures to root cause within days, distinguishing microarchitectural bugs from testbench and reference-model issues.

What you will bring

Must-haves

2 to 5 years of processor or CPU verification experience with SystemVerilog and UVM.
Deep understanding of processor microarchitecture: pipelines, hazard handling, branch prediction, and out-of-order concepts.
Experience with ISA-level verification: instruction-stream generation and checking against architectural models.
Knowledge of exception, interrupt, and privilege-mode behavior and how to verify precise delivery.
Familiarity with memory consistency models and techniques for verifying ordering and atomicity.
Strong debug skills for tracing failures through pipeline stages and architectural state.
Ability to read ISA specifications and derive verification requirements from them.

Nice-to-haves

Experience with riscv-formal or similar formal ISA verification frameworks.
Knowledge of RISC-V, ARM, or x86 ISA specifics.
Exposure to cache coherence verification for multicore designs.
Familiarity with hypervisor or virtualization extensions verification.