Principal ASIC Verification Engineer

ASIC Verification Engineer Principal (L7 equivalent), org-wide scope 12+ years

Other levels: ASIC Verification Engineer Senior ASIC Verification Engineer Staff ASIC Verification Engineer Lead ASIC Verification Engineer Junior ASIC Verification Engineer

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The job description

Tech stack. SystemVerilog, UVM, formal verification (Jasper, VC Formal), emulation (Palladium, Zebu), coverage-driven methodology, Python, EDA tool evaluation

About the role

You will serve as the technical authority for verification at a semiconductor company shipping multiple complex SoCs per year. Principal engineers here do not just verify blocks; they define how verification is done across the organization, setting signoff criteria, coverage methodology, and tool strategy that every project follows. Your influence spans projects and teams: architects consult you on verifiability before RTL exists, executives trust your tapeout readiness assessments when millions of dollars ride on the decision, and the verification methodology of the company carries your fingerprints. You will evaluate emerging technologies, kill weak methodologies before they waste project time, and build the senior engineers who will carry the discipline forward. This is the role where verification stops being a project activity and becomes an organizational capability.

What you will achieve

Define the org-wide verification methodology and signoff criteria, raising the coverage and quality bar across all concurrent projects.
Reduce silicon respins caused by verification escapes by 50 percent year over year through stronger planning standards, review processes, and coverage metrics.
Lead technical evaluation and adoption of new verification technologies (formal apps, portable stimulus, ML-assisted coverage) with measured ROI on project schedules.
Set the debug and triage playbook for multi-block and full-chip failures, cutting average root-cause time on critical issues in half.
Build the next generation of verification leaders by mentoring senior and staff engineers and running the technical interview loop for verification hiring.

What you will bring

Must-haves

12 or more years of ASIC verification experience across multiple successful tapeouts at advanced nodes.
Recognized expertise in coverage-driven verification methodology, including defining signoff criteria used by multiple projects.
Deep knowledge of both simulation-based verification and formal methods, with judgment on when each applies.
Experience influencing verification strategy across teams or business units, not just within one project.
Strong partnership skills with design, architecture, DFT, and post-silicon teams at the director level and above.
Track record of evaluating EDA tools and flows and driving adoption decisions with data.
Ability to present tapeout risk assessments to executive leadership with clarity and candor.

Nice-to-haves

Published papers, conference talks, or patents in verification methodology.
Experience with safety-critical or automotive (ISO 26262) verification flows.
Background in emulation or FPGA prototyping strategy for large SoCs.
Background in post-silicon debug to inform pre-silicon methodology.