Principal ASIC Design Verification Engineer

ASIC Design Verification Engineer Principal (L7 equivalent), org-wide scope 12+ years

Other levels: ASIC Design Verification Engineer Senior ASIC Design Verification Engineer Staff ASIC Design Verification Engineer Lead ASIC Design Verification Engineer Junior ASIC Design Verification Engineer

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The job description

Tech stack. SystemVerilog/UVM methodology, formal verification strategy, emulation (Palladium/Zebu), coverage signoff frameworks, verification IP, CI for silicon flows

About the role

You will be the company-wide technical authority for design verification at a semiconductor company scaling from single programs to a portfolio of chips. You will define what "done" means across every tapeout: the methodologies, signoff criteria, and tool investments that keep verification quality rising as complexity compounds. Your scope spans all design teams, your judgment sets the risk posture of every silicon release, and your mentorship shapes the next generation of verification leaders.

What you will achieve

Establish an org-wide verification signoff standard (coverage floors, formal proof requirements, regression quality gates) adopted across all active programs within your first year.
Drive first-silicon success on every program in your tenure by institutionalizing escape root-cause analysis that feeds back into methodology improvements, not just one-off RTL patches.
Deliver a unified UVM and VIP reuse strategy that cuts testbench development time by 30 percent or more across programs, measured against historical baselines.
Reduce schedule risk by introducing emulation and formal-first flows where they demonstrably shorten verification closure on complex subsystems, with ROI tracked per program.
Build verification capability at scale by mentoring staff and senior engineers into technical leaders and by setting the hiring bar for the entire function.

What you will bring

Must-haves

12+ years of ASIC verification experience with multiple first-silicon successes across complex SoCs or accelerators.
Recognized expertise in at least two of: constrained-random UVM verification, formal verification, emulation-based verification, or low-power signoff.
Track record of defining verification methodology or signoff standards used across multiple teams or programs, with measurable quality or schedule impact.
Deep understanding of the full silicon flow: RTL, synthesis, DFT, physical design constraints, and how each shapes verification strategy and risk.
Executive-level communication: you explain verification risk and residual escape probability to leadership in plain, quantified terms that drive decisions.
History of growing senior engineers into staff-level technical leaders through sustained mentorship.
Strategic judgment about tools and methodology bets: you know what to adopt, what to skip, and how to prove the difference.

Nice-to-haves

Published or patented work in verification methodology or formal methods.
Experience standing up verification for a new process node or a new product category.
Familiarity with safety-critical (ISO 26262) or security certification flows.
Vendor and industry relationships that keep the company ahead of EDA roadmap changes.