Pre-Silicon Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, gate-level simulation, SDF back-annotation, static timing-aware verification, power-aware simulation, ECO validation

About the role

You will own the final pre-silicon verification gates at a fabless chip company: the checks that run after synthesis and place-and-route, where the design that tapes out is proven equivalent to the design you verified. Working hand in hand with backend designers, you will catch the timing, reset, and power-intent bugs that RTL simulation cannot see. Your work is the reason first silicon behaves like the model, and your checklist is the last thing reviewed before the tapeout decision. You are the final technical conscience of the program: when you sign off, the company commits millions of dollars to masks, and your checklist is what makes that decision defensible.

What you will achieve

Deliver gate-level simulation campaigns with SDF back-annotation that pass at 100 percent on the final netlist before tapeout signoff.
Drive equivalence confidence by validating every functional ECO through targeted re-simulation, with zero ECOs taping out unverified.
Ship power-aware simulation results proving correct behavior across power modes (shutdown, retention, DVFS transitions) in partnership with low-power designers.
Cut late-stage surprises by running reset and initialization sequences on the gate-level netlist, catching X-propagation and reset-domain issues before signoff.
Reduce signoff risk by maintaining a pre-silicon checklist (timing-clean simulations, zero-X checks, DFT-mode functional tests) that formally gates the tapeout decision.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience including gate-level or post-synthesis verification work on real tapeouts.
Strong SystemVerilog/UVM fundamentals plus practical experience with SDF-annotated simulation and its performance challenges.
Understanding of static timing concepts (setup/hold, clock skew, multi-cycle paths) and how they affect what simulation can prove.
Experience debugging X-propagation, reset sequencing, and initialization issues on gate-level netlists.
Familiarity with power intent (UPF/CPF) and power-aware simulation flows.
Ability to collaborate with physical design and DFT engineers on timing and scan-related verification issues.
Composure under tapeout pressure: the final gate-level regressions always find something, and you triage calmly and correctly.

Nice-to-haves

Experience with formal equivalence checking between RTL and netlist.
Knowledge of scan insertion and ATPG concepts as they interact with functional verification.
Scripting skills for automating netlist simulation setup and result triage.
Familiarity with multi-corner and multi-mode timing signoff concepts.