Power/Performance CPU Design Engineer

About the role

You will specialize in power-efficient CPU design at a semiconductor company, implementing the clock gating, power gating, DVFS, and adaptive techniques that let processors deliver maximum performance within strict power envelopes. Power/performance designers own the implementation of the power management architecture: the power controller logic, the isolation and retention structures, the telemetry collection, and the careful RTL practices that minimize wasted energy everywhere. Your work directly determines the product's battery life, thermal behavior, and datacenter operating costs.

What you will achieve

• Implement power management logic including power controllers, DVFS interfaces, clock and power gating controls, and idle-state entry and exit sequencing with correct, robust behavior under all transition scenarios.
• Write complete power-intent specifications using UPF for your blocks, defining power domains, isolation strategies, retention registers, level shifters, and power switch controls accurately.
• Optimize RTL for power through aggressive clock gating, operand isolation, data-driven gating, and activity-aware design, quantifying savings rigorously with power analysis flows rather than assuming them.
• Verify low-power behavior including power state transitions, reset sequencing across power domains, isolation correctness, and retention restore, closing the specialized coverage this domain requires.
• Partner with architects and physical design engineers on the realization of power structures, ensuring the design intent for gating, isolation, and power delivery survives intact through implementation.
• Validate power consumption on silicon against pre-silicon targets, correlating measurements with estimates and refining both design practices and estimation methodology for future programs.

What you will bring

Must-haves

• 5 to 8 years of experience in low-power digital design with shipped products in power-constrained client, mobile, or datacenter markets.
• Deep knowledge of low-power techniques: clock gating, power gating, multi-Vt optimization, DVFS, retention strategies, and isolation.
• Fluency in power intent specification with UPF and hands-on experience with low-power implementation and verification flows.
• Strong SystemVerilog design skills with power-aware coding practices embedded in everyday work.
• Experience with power analysis tools and methodologies from early RTL estimation through sign-off correlation.
• Understanding of the verification challenges unique to low-power design including power-aware simulation and state transition coverage.
• Data-driven mindset with the discipline to measure power impact rather than assume it, and the honesty to report when a technique does not pay off.

Nice-to-haves

• Experience with adaptive techniques such as adaptive voltage scaling, in-situ timing monitors, or dynamic power policies.
• Knowledge of thermal management architectures and their interaction with power control loops.
• Familiarity with advanced process node power challenges including leakage dominance and power density limits.
• Exposure to system-level power modeling and workload-driven power analysis.