Power Management Mixed Signal Designer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Cadence Virtuoso, Spectre, Simplis, Calibre, Verilog-AMS, high-voltage BCD or CMOS PDKs, lab power instrumentation

About the role

You will design power management ICs at a fabless semiconductor company whose products power everything from processors to sensors. The team builds DC-DC converters, LDOs, and power-path circuits where efficiency, transient response, and stability are the entire product. This role matters because every watt your converter saves extends battery life or cuts system thermals, and customers choose PMICs on measured efficiency curves. You will work with systems and applications engineers on reference designs, since a PMIC is only as good as the board around it, and your efficiency numbers have to hold up in customer hands. You will also validate transient response on the bench with real load steps, since Simplis models of control-loop stability must be proven against actual silicon behavior.

What you will achieve

Ship one to two power management blocks per year (buck, boost, buck-boost, LDO, or load switch) with measured efficiency meeting the target curve across load and line on first silicon.
Drive transient performance: deliver converters with load-step response (undershoot, overshoot, settling) inside the spec that keeps the powered SoC out of reset, verified in silicon.
Reduce system cost through integration: higher switching frequencies, integrated FETs, and DVS support that shrink the external BOM (inductor and capacitor size) for customers.
Own stability sign-off: loop analysis across all modes (PWM, PFM, dropout), with phase margin verified in simulation and confirmed by lab measurement on silicon.
Cut EMI and noise issues by designing with spread-spectrum, slew control, and layout discipline, then validating conducted emissions against the target standard.

What you will bring

Must-haves

2-5 years designing power management circuits (DC-DC converters, LDOs, charge pumps, or references) with tapeout and measured efficiency results.
Deep understanding of converter control: voltage-mode and current-mode control, loop compensation, stability analysis, and mode transitions.
Experience with power FET design and driving: gate drive, dead time, shoot-through prevention, and switching loss optimization.
Fluency in efficiency analysis: conduction, switching, gate drive, and quiescent losses budgeted and measured across load.
Knowledge of inductor and capacitor selection tradeoffs and how they interact with your control loop.
Lab skills with power instrumentation: efficiency measurement, load transient testing, and thermal characterization.

Nice-to-haves

Experience with digital control loops or DVS/DVFS interfaces to SoCs.
Knowledge of battery charging circuits or USB power delivery.
Familiarity with high-voltage BCD processes.