Power Management IC (PMIC) Design Engineer

Analog IC Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. DC-DC converters, buck/boost topologies, LDOs, power sequencing, load-transient response, loop compensation, BCD processes, Cadence Virtuoso, Simplis

About the role

You will join a power management semiconductor company designing PMICs that feed processors, sensors, and radios in mobile and industrial systems. The team owns the full power tree: conversion, sequencing, protection, and telemetry, integrated on one die. This role matters because power efficiency and transient response are the specs customers test first, and winning them wins the socket for the entire platform. Efficiency and EMI regulations tighten every year, and the team that stays ahead of them owns the market.

What you will achieve

Ship buck, boost, and LDO blocks that hit efficiency, load-transient, and PSRR targets on first silicon across line, load, and temperature
Design loop compensation that stays stable across the full operating envelope, eliminating oscillation escapes in validation
Cut quiescent current and standby power to class-leading levels, directly improving the end product's battery-life story
Deliver power-sequencing and fault-protection schemes (OVP, OCP, thermal shutdown) that pass system-level abuse testing without nuisance trips
Drive silicon correlation between Simplis and Spectre models and bench measurements, tightening models so the next design needs fewer spins
Support customer power-tree bring-up, resolving board-level interactions between your PMIC and the customer's load profile
Publish application notes and reference designs that accelerate customer adoption and shorten their time to production

What you will bring

Must-haves

2-5 years designing power management circuits with at least one shipped PMIC or converter product
Deep understanding of switching converter operation: inductor current modes, switching losses, EMI, and control schemes (voltage mode, current mode, COT)
Fluency in loop stability analysis and compensation design for both switching and linear regulators
Experience with protection and sequencing circuits, including fault detection, retry behavior, and safe startup under load
Proficiency in Cadence Virtuoso and Spectre; Simplis or similar time-domain power simulation experience strongly valued
Practical knowledge of power device layout: DMOS structures, current density, thermal paths, and bond-wire limits
B.S. or M.S. in Electrical Engineering with a power electronics or analog circuits emphasis

Nice-to-haves

Experience with digital control loops or PMBus/I2C telemetry in PMICs
Familiarity with GaN or high-frequency switching techniques for size reduction
Prior work on battery chargers, USB-PD, or automotive power products