Power Design Verification Engineer

About the role

You will own power-aware verification at a semiconductor company where battery life and thermal limits are product-defining. Working with low-power architects and RTL designers, you will prove that power intent is implemented correctly: domains shut down and wake up cleanly, isolation and retention work, and the chip never draws power it should not. Your signoff certifies that the power architecture works as designed, not just as simulated without power, and your checkers watch every domain transition. A chip that computes correctly but burns its power budget is a failed product, and your signoff is the proof that the power architecture holds under every mode and transition.

What you will achieve

• Deliver power-aware simulation campaigns proving correct behavior across all power modes (active, idle, retention, shutdown) for your assigned domains.
• Drive low-power structural checks (isolation, level-shifter, retention verification) to clean results on every RTL drop, with waivers reviewed by the power architect.
• Ship verification of power sequencing: power-up, power-down, and DVFS transitions proven glitch-free and protocol-correct in partnership with designers.
• Cut power-bug escape risk by building power-state-aware checkers and coverage that track legal and illegal power-state transitions across the design.
• Reduce signoff uncertainty by correlating power-aware simulation results with the UPF intent, flagging any divergence between intent and implementation before tapeout.

What you will bring

Must-haves

• 2 to 5 years of ASIC verification experience including power-aware (UPF/CPF) verification work on real designs.
• Strong SystemVerilog/UVM skills with hands-on power-aware simulation experience, not just theory.
• Deep understanding of low-power design techniques: power gating, isolation, retention, level shifters, DVFS, and multi-VDD architectures.
• Ability to read and debug UPF power intent and to write power-aware assertions and checkers that enforce it.
• Experience debugging power-related failures: X-propagation from unpowered domains, isolation glitches, and retention corruption.
• Collaborative approach with power architects and physical design engineers on power-intent signoff.
• Rigor about completeness: power bugs hide in the transitions nobody thought to test, and you test them.

Nice-to-haves

• Familiarity with power estimation or power-performance verification.
• Experience with formal low-power checks or static power-intent verification.
• Knowledge of always-on domains and their unique verification challenges.
• Exposure to thermal-aware or IR-drop-aware verification concepts.