PLL/DLL Analog Design Engineer

Analog Design Engineer Senior (L5 equivalent) 5-8 years

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The job description

Tech stack. PLL and DLL design, VCOs, phase noise analysis, Cadence Virtuoso, SpectreRF, loop filter design, frequency synthesizers, jitter budgeting

About the role

You will design phase-locked loops and delay-locked loops at a semiconductor company, creating the frequency synthesizers and clock generators that time every digital operation on the chip. PLL designers work in a domain where picoseconds matter: their loops must generate clean, stable clocks with minimal jitter and spurious tones across process, voltage, and temperature variation. You will design VCOs, charge pumps, loop filters, and dividers, analyze loop dynamics rigorously, and validate phase noise and jitter on silicon. You will also architect the jitter budgeting flow from reference clock to output, allocating phase-noise contributions across the VCO, charge pump, and divider so every block meets its share of the system target.

What you will achieve

Design complete PLLs including phase detectors, charge pumps, loop filters, VCOs, and dividers meeting phase noise, spurious, lock time, and power specifications.
Design low-jitter VCOs using LC or ring topologies selected through quantitative phase noise, tuning range, and power analysis for the application requirements.
Analyze loop dynamics including stability, bandwidth optimization, and transient response, designing loop filters that balance noise suppression against lock time and tracking.
Design DLLs for clock alignment and deskew applications with precise delay control and robust operation across PVT variation.
Model jitter budgets end to end, allocating contributions from reference noise, VCO noise, charge pump mismatch, and supply noise, and verifying the budget through simulation.
Validate PLLs and DLLs on silicon with phase noise, jitter, spurious, and lock-time measurements, correlating against models and debugging discrepancies systematically.

What you will bring

Must-haves

5 to 8 years of experience in PLL, DLL, or frequency synthesizer design with shipped products.
Deep understanding of PLL theory: loop dynamics, phase noise mechanisms, spurious sources, and their mitigation.
Strong circuit design skills for VCOs, charge pumps, phase detectors, dividers, and loop filters.
Experience with phase noise analysis using SpectreRF PNOISE and jitter computation methodologies.
Knowledge of supply noise sensitivity and isolation techniques critical for PLL performance.
Bench measurement expertise for phase noise, jitter, and spurious characterization.
Understanding of system-level clocking requirements and jitter specifications for target applications.

Nice-to-haves

Experience with fractional-N synthesizers, digital PLLs, or all-digital architectures.
Familiarity with spread-spectrum clocking or clock-data recovery applications.
Knowledge of advanced VCO techniques such as class-C operation or switched-capacitor tuning.
Background in high-frequency mmWave synthesizer design.