PLL/Clocking Mixed Signal Designer

Mixed Signal Design Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. Cadence Virtuoso, SpectreRF, MATLAB PLL modeling, Calibre, EMX, Verilog-AMS, Python

About the role

You will design phase-locked loops and clocking circuits at a fabless semiconductor company where every high-speed interface and converter depends on your clock quality. The team owns integer-N and fractional-N PLLs, clock distribution, and jitter cleanup circuits that set the timing budget for the whole chip. This role matters because phase noise and jitter from your PLL directly limit SerDes BER, ADC SNR, and RF EVM, making your block the quiet foundation everything else stands on. You will support every team that consumes your clocks, from SerDes to converters, and your phase noise plots will be reviewed as carefully as any datasheet spec.

What you will achieve

Ship one to two tapeout-ready PLLs per year (integer-N, fractional-N, or multiplying DLL) with measured integrated jitter and phase noise meeting the system budget with margin on first silicon.
Drive fractional spur performance: deliver fractional-N PLLs with reference spurs and fractional spurs below the system mask across the full output frequency range.
Reduce clock distribution jitter by designing low-noise dividers, buffers, and duty-cycle correction that hold the end-to-end jitter budget from PLL output to the load.
Own PLL behavioral modeling in MATLAB: phase-domain and time-domain models that predict lock time, phase noise, and spur levels within 3 dB of silicon before tapeout.
Cut bring-up risk by writing your own PLL test plans: phase noise measurement, jitter integration, lock-time characterization, and supply-pushing tests automated in the lab.

What you will bring

Must-haves

2-5 years designing PLLs or clocking circuits (VCO, charge pump, loop filter, dividers, or full PLL) with tapeout and measured phase noise results.
Deep understanding of PLL theory: loop dynamics, phase noise transfer, reference spurs, fractional-N quantization noise, and delta-sigma modulator design.
VCO design experience: LC and ring oscillators, tuning range versus phase noise tradeoffs, and supply pushing minimization.
Fluency in SpectreRF PNOISE and periodic analyses for jitter and phase noise simulation.
Loop filter design skills: passive and active filters, stability analysis, and component sensitivity.
Lab measurement skills: phase noise analyzers, jitter measurement, and lock-time characterization.

Nice-to-haves

Experience with spread-spectrum clocking or jitter attenuation PLLs.
Knowledge of clock distribution networks and skew management at the top level.
Familiarity with all-digital PLLs or injection-locked techniques.