Physical Design Engineer (CPU)

CPU Design Engineer Senior (L5 equivalent) 5-8 years

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The job description

Tech stack. Place and route, physical synthesis, static timing analysis, clock tree synthesis, power grid design, EM and IR analysis, EDA tools, TCL and Python scripting

About the role

You will implement the physical design of CPU blocks at a semiconductor company, turning synthesized netlists into manufacturable layouts that meet timing, power, area, and reliability targets. Physical design engineers own the backend flow end to end: floorplanning, placement, clock tree synthesis, routing, and sign-off, applied to some of the most challenging blocks in the industry with high frequencies, dense logic, aggressive power constraints, and unforgiving schedules. Your layouts become the actual silicon that ships to customers.

What you will achieve

Deliver physical implementation of CPU blocks or partitions from netlist to tapeout-ready GDSII, meeting timing, power, area, DRC, and reliability targets on aggressive program schedules.
Develop floorplans that balance timing closure, routing congestion, power delivery integrity, and thermal considerations, applying your understanding of the underlying logic structure to guide placement decisions.
Implement robust clock distribution including clock tree synthesis for high-frequency designs with tight skew, latency, and variation-tolerance requirements.
Close timing across multi-corner, multi-mode scenarios, resolving violations systematically through placement refinement, buffering, layer assignment, useful skew, and collaboration with front-end designers on logic restructuring.
Ensure power integrity through power grid design, electromigration and IR drop analysis, and decap planning, with particular attention to high-activity CPU blocks with severe di/dt behavior.
Drive physical verification and DFM closure including DRC, LVS, antenna rules, and density requirements, delivering clean, manufacturable layouts ready for tapeout.

What you will bring

Must-haves

5 to 8 years of experience in physical design, physical synthesis, or backend implementation with high-performance blocks and completed tapeouts.
Deep expertise in place-and-route flows, static timing analysis, and systematic timing closure methodologies.
Strong understanding of clock tree design, skew management, and variation-tolerant clocking for high-frequency processors.
Knowledge of power integrity engineering including electromigration, IR drop, power grid design, and decap strategy.
Familiarity with advanced process node challenges including variation, complex design rules, DFM requirements, and multi-patterning implications.
Scripting skills in TCL and Python for flow automation, data analysis, and custom tool development.
Collaboration skills for working productively with front-end designers on timing-driven logic changes and constraint refinement.

Nice-to-haves

Experience with 3D integration, chiplet physical design, or advanced packaging technologies.
Knowledge of custom clocking techniques such as useful skew optimization or adaptive clocking.
Background in full-chip integration, top-level floorplanning, or hierarchical implementation methodologies.
Familiarity with thermal analysis and its interaction with physical implementation choices.