Networking ASIC Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, Ethernet (PCS/MAC), PCIe, packet generators, traffic modeling, Synopsys VCS, SVA, Python

About the role

You will verify networking silicon at a fabless semiconductor company building switch, router, or SmartNIC chips that move packets at hundreds of gigabits per second. Networking verification is traffic verification: line-rate packet flows, congestion scenarios, QoS scheduling, and protocol compliance across Ethernet, PCIe, and fabric interfaces. Your testbenches generate the traffic patterns that prove the chip forwards, classifies, and schedules packets correctly under the worst conditions the network can produce. You will think in terms of traffic mixes and congestion events rather than individual transactions, building scoreboards that track millions of packets end to end. When the chip sustains line rate under adversarial traffic without dropping a priority packet, your verification proved it could.

What you will achieve

Build packet-level UVM testbenches with traffic generators that sustain line-rate stimulus and verify forwarding correctness across millions of packets.
Verify QoS and scheduling behavior under congestion, proving priority, shaping, and drop policies match the architecture specification.
Close protocol compliance on Ethernet (PCS/MAC) and PCIe interfaces using VIP and SVA checkers, with zero compliance violations at signoff.
Create scoreboards that track packets end to end through pipelines, catching ordering, duplication, and loss bugs in complex switching fabrics, with per-flow statistics that pinpoint exactly where packets go wrong.
Drive performance verification proving the chip meets its packets-per-second and latency targets under worst-case traffic mixes, and publish the performance characterization data that marketing and customers rely on for datasheet claims.

What you will bring

Must-haves

2 to 5 years of verification experience on networking, communications, or high-throughput datapath designs.
Strong SystemVerilog and UVM skills with experience building packet-based stimulus and scoreboards.
Working knowledge of Ethernet protocols (MAC, PCS, FEC) and packet formats (VLAN, MPLS, VXLAN).
Familiarity with PCIe for host interfaces on networking chips.
Understanding of QoS concepts: traffic shaping, scheduling algorithms, and congestion management.
SVA skills for protocol checking on high-speed interfaces.
Scripting ability for traffic analysis, performance measurement, and results automation.

Nice-to-haves

Experience with P4-programmable pipelines or programmable parser verification.
Knowledge of RDMA (RoCE) or data-center networking protocols.
Exposure to system-level testing with real network traffic captures.
Familiarity with 800G Ethernet and next-generation SerDes standards.