Mixed-Signal Verification Engineer

ASIC Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog, UVM, AMS simulation (Spectre, XA), wreal modeling, DMS (digital mixed-signal), SVA, Cadence Xcelium, Python

About the role

You will verify the analog-digital boundary at a semiconductor company building chips where PLLs, ADCs, DACs, and SerDes PHYs meet digital control logic. Mixed-signal verification proves that the digital side correctly drives and interprets analog behavior: calibration sequences, lock detection, data converters, and power management handshakes. Your wreal models and AMS testbenches are what let the team verify these interactions in simulation instead of discovering them on the bench. You will work at the intersection of two engineering cultures, translating analog specifications into digital verification requirements and building the models that make co-simulation fast enough to be useful. The bugs you catch at this boundary are the ones that neither pure-digital nor pure-analog verification can see.

What you will achieve

Build mixed-signal testbenches that verify digital control of analog blocks (PLL lock sequences, ADC calibration, DAC output checks) across process corners.
Develop wreal behavioral models of analog blocks that run 100x faster than transistor-level simulation while preserving interface-accurate behavior.
Verify analog-digital interfaces (control registers, status handshakes, interrupt generation) with SVA checkers adapted to mixed-signal timing.
Drive DMS (digital mixed-signal) simulation flows that co-simulate digital RTL with analog behavioral models for full-chip mixed-signal signoff, and validate the flow against transistor-level reference runs on critical paths.
Catch interface bugs between analog and digital teams early, reducing mixed-signal respins caused by misinterpreted specifications.

What you will bring

Must-haves

2 to 5 years of mixed-signal or analog-adjacent verification experience with SystemVerilog.
Understanding of analog fundamentals: PLLs, ADCs, DACs, bandgaps, and SerDes building blocks at a behavioral level.
Experience with wreal modeling or other real-number behavioral modeling techniques for analog blocks.
Familiarity with AMS simulation tools (Spectre, XA, or equivalent) and DMS co-simulation flows.
Strong UVM skills for building the digital side of mixed-signal testbenches.
Ability to read analog block specifications and derive digital verification requirements from them.
Debugging skills spanning digital waveforms and analog behavioral traces.

Nice-to-haves

Experience with Cadence Virtuoso or similar analog design environments.
Knowledge of calibration and trimming flows for data converters.
Exposure to EM/IR or other physical effects that cross the analog-digital boundary.
Experience with aging and reliability simulation for analog blocks.