Mixed-Signal Design Verification Engineer

ASIC Design Verification Engineer Mid-level (L4 equivalent) 2-5 years

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The job description

Tech stack. SystemVerilog/UVM, real-number modeling (wreal), AMS simulation, Verilog-AMS concepts, analog/digital interface verification, CDC across domains

About the role

You will verify the boundary where analog meets digital at a semiconductor company: the ADCs, DACs, PLLs, and sensor interfaces whose digital control logic must be proven correct even though the analog behavior is modeled, not simulated. Working with both analog and digital designers, you will build the models and checkers that prove the digital side handles every analog event: lock, calibration, conversion, and fault. Your work de-risks the interfaces most likely to fail in silicon, and your models are the contract between two design disciplines. The analog designers trust your models to represent their circuits fairly, and the digital designers trust your checkers to catch real failures, which makes you the bridge both sides rely on.

What you will achieve

Deliver real-number models (wreal) of analog blocks accurate enough for digital verification, validated against analog designer expectations and corner behavior.
Drive verification of analog and digital control sequences (calibration, lock acquisition, power-up sequencing) to 100 percent functional coverage.
Ship checkers for data-converter interfaces proving correct sample timing, data integrity, and error handling across PVT-modeled corners.
Cut mixed-signal debug time by building transaction-level visibility into analog events within the digital testbench, so failures read as sequences, not mysteries.
Reduce silicon risk by verifying fault and out-of-range behavior (loss of lock, over-range inputs, supply droops) that pure digital simulation ignores.

What you will bring

Must-haves

2 to 5 years of ASIC verification experience with exposure to mixed-signal designs or analog interfaces.
Strong SystemVerilog/UVM skills with practical experience in real-number modeling for analog blocks.
Understanding of common mixed-signal blocks at the behavioral level: PLLs, ADCs, DACs, bandgaps, and LDOs.
Experience verifying control sequences and state machines that interact with analog behavior and timing.
Ability to work across disciplines: translating analog designer knowledge into verifiable digital requirements and checkers.
Familiarity with AMS simulation concepts and an honest understanding of the limits of digital-centric verification.
Curiosity about the analog side: you ask analog designers how things really behave instead of assuming the model is truth.

Nice-to-haves

Experience with Verilog-AMS or SystemVerilog-AMS modeling.
Knowledge of DFT and test considerations for mixed-signal blocks.
Familiarity with sensor interfaces (temperature, voltage, current monitoring) and their digital readouts.
Exposure to post-silicon correlation between modeled and measured analog behavior.